Handbook of 3D Integration.Vol.4

PART I: DESIGN
3D Design Styles
Design Enablement and Advantages of Ultra-Fine Pitched 3D-Stacked Integrated Circuits
Wyoming Case Study
IBM Interposers
Interposer Interconnect Circuits
Signal Integrity for 3D
Power Integrity for 3D
2.5D/3D Design Flow
Monolithic 3D
EDA for 3D
3D Memories
3D Clock Distribution
PART II: TEST
Cost Modelling for 2.5D and 3D Stacked ICs
Interconnect Testing for 2.5D and 3D Stacked ICs
Pre-Bond Testing Through Direct Probing of Large-Array Fine-Pitch Micro-Bumps
3D Design-for-Test Architecture
Optimization of Test-Access Architectures and Test Scheduling for 3D ICs
IEEE P1838 3D Test Access Standard-in-Development
Test and Debug Strategy for TSMC CoWoS Stacking Process Based Heterogeneous 3D IC: A Silicon Case Study
PART III: THERMAL MANAGEMENT
Thermal Challenges and Emerging Solutions for 3D and 2.5D IC
Thermal Modeling and Experimental Model Validation for 3D Stacked ICs
Thermal Design for 3D ICs with Micro-Fluidics

Paul D. Franzon is currently the Cirrus Logic Distinguished Professor of Electrical and Computer Engineering and Director of Graduate programs in ECE at North Carolina State University. He earned his PhD from the University of Adelaide, Adelaide, Australia. He has also worked at AT&T Bell Laboratories, DSTO Australia, Australia Telecom and four companies he cofounded, Communica, LightSpin Technologies, Polymer Braille Inc. and Avago. His current interests include applying machine learning to EDA, building machine learning accelerators, neuromorphic computing, RFID, advanced packaging, 3DICs and secure chip design. He has lead several major efforts and published over 300 papers in these areas. In 1993 he received an NSF Young Investigators Award, in 2001 was selected to join the NCSU Academy of Outstanding Teachers, in 2003, selected as a Distinguished Alumni Professor, received the Alcoa Research Award in 2005, and the Board of Governors Teaching Award in 2014. He served with the Australian Army Reserve for 13 years as an Infantry Soldier and Officer. He is a Fellow of the IEEE.
 
Erik Jan Marinissen is Principal Scientist at IMEC in Leuven, Belgium and part-time Visiting Researcher at Eindhoven University of Technology in the Netherlands. Prior to IMEC, he worked at NXP Semiconductors and Philips Research in Eindhoven, Nijmegen, and Sunnyvale (CA). His research on IC test and design-for-test covers topics as diverse as modular test of SoCs, 3D-stacked ICs, CMOS below 10nm, silicon photonics, and STT-MRAMs. Marinissen received the MSc degree in computing science and the PDEng degree in software technology from Eindhoven University of Technology. An IEEE Fellow, he is a co-author of more than 275 journal and conference papers and a co-inventor of 18 granted patent families. He served as editor-in-chief of IEEE Std 1500 and as founder/chair of the IEEE Std P1838 Working Group on 3D-SIC test access. In 2019-2021, he serves on the Board of Governors of IEEE