Handbook of 3D Integration.Vol.3

3D IC INTEGRATION SINCE 2008
3D IC Nomenclature
Process Standardization
The Introduction of Interposers (2.5D)
The Foundries
Memory
The Assembly and Test Houses
3D IC Application Roadmaps
 
KEY APPLICATIONS AND MARKED TRENDS FOR 3D INTEGRATION AND INTERPOSER TECHNOLOGIES
Introduction
Advanced Packaging Importance in the Semiconductor Industry is Growing
3D Integration-Focused Activities - The Global IP Landscape
Applications, Technology, and Market Trends
 
ECONOMIC DRIVERS AND IMPEDIMENTS FOR 2.5D/3D INTEGRATION
3D Performance Advantages
The Economics of Scaling
The Cost of Future Scaling
Cost Remains the Impediment to 2.5D and 3D Product Introduction
 
INTERPOSER TECHNOLOGY
Definition of 2.5D Interposers
Interposer Drivers and Need
Comparison of Interposer Materials
Silicon Interposers with TSV
Lower Cost Interposers
Interposer Technical and Manufacturing Challenges
Interposer Application Examples
Conclusions
 
TSV FORMATION OVERVIEW
Introduction
TSV Process Approaches
TSV Fabrication Steps
Yield and Reliability
 
TSV UNIT PROCESSES AND INTEGRATION
Introduction
TSV Process Overview
TSV Unit Processes
Integration and Co-Optimization of Unit Processes in Via Formation Sequence
Co-Optimization of Unit Processes in Backside Processing and Via-Reveal Flow
Integration and Co-Optimization of Unit Processes in Via-Last Flow
Integration with Packaging
Electrical Characterization of TSVs
Conclusions
 
TSV FORMATION AT ASET
Introduction
Via-Last TSV for Both D2D and W2W Processes in ASET
TSV Process for D2D
TSV Process for W2W
Conclusions
 
LASER-ASSISTED WAFER PROCESSING: NEW PERSPECTIVES IN THROUGH-SUBSTRATE VIA DRILLING AND REDISTRIBUTION LAYER DEPOSITION
Introduction
Laser Drilling of TSVs
Direct-Write Deposition of Redistribution Layers
Conclusions and Outlook
 
TEMPORARY BONDING MATERIAL REQUIREMENTS
Introduction
Technology Options
Requirements of a Temporary Bonding

Philip Garrou is a consultant and expert witness in the field of IC packaging materials and applications, prior to which he was Dir. of Technology and Business Dev. for Dow Chemicals' Electronic Materials business. Dr. Garrou is a Fellow of IEEE and IMAPS and served as President of the IEEE CPMT Society and IMAPS. He has co-authored 3 microelectronics texts and 100+ publications. He is Assoc. Ed. and author of the weekly blog "Insights from the Leading Edge" for Solid State Technology and has co-authored 3DIC reports for both TechSearch and Yole.
 
Mitsumasa Koyanagi is Professor in New Industry Creation Hatchery Center (NICHe) and Director in GINTI (Global Integration Initiative) at Tohoku University, Japan. After his PhD in electrical engineering he joined the Central Research Laboratory of Hitachi where he was engaged in the research on semiconductor memories. After a three-year stay at the Xerox Palo Alto Research Center in California, USA, he became Professor in the Research Center for Integrated Systems at Hiroshima University, Japan. Mitsumasa Koyanagi received numerous awards, including the IEEE Jun-ichi Nishizawa Medal and the National Medal with Purple Ribbon in Japan.
 
Peter Ramm is head of the department Heterogeneous System Integration of Fraunhofer EMFT in Munich, Germany, where he is responsible for the key competence "Si Processes, Device and 3D Integration". He received the physics and Dr. rer. nat. degrees from the University of Regensburg and subsequently worked for Siemens in the DRAM facility where he was responsible for the process integration. In 1988 he joined Fraunhofer IFT in Munich, focusing for more than 25 years on 3D integration technologies. Peter Ramm is coauthor of over 100 publications and 24 patents and editor of Wiley´s "Handbook of Wafer Bonding". He received the "Ashman Award 2009" from IMAPS "For Pioneering Work on 3D IC Stacking and Integration".