Hardware Acceleration of EDA Algorithms
Custom ICs, FPGAs and GPUs
(Sprache: Englisch)
This book deals with the acceleration of EDA algorithms using hardware platforms such as FPGAs and GPUs. Widely applied CAD algorithms are evaluated and compared for potential acceleration on FPGAs and GPUs. Coverage includes discussion of conditions under...
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This book deals with the acceleration of EDA algorithms using hardware platforms such as FPGAs and GPUs. Widely applied CAD algorithms are evaluated and compared for potential acceleration on FPGAs and GPUs. Coverage includes discussion of conditions under which it is preferable to use one platform over another, e.g., when an EDA problem has a high degree of data parallelism, the GPU is typically the preferred platform, whereas when the problem has more control, an FPGA may be preferred. Results are presented for the acceleration of several CAD algorithms (fault simulation, fault table generation, model card evaluation in SPICE, Monte Carlo statistical static timing analysis), demonstrating speedups from 30X to 800X.
This book serves as a valuable guide on how best to leverage parallelism to accelerate CAD algorithms. It also presents a methodology to extract automatically SIMD parallelism from regular uniprocessor code. With this approach, uniprocessor code can automatically be converted to GPU code, allowing for significant acceleration. This approach is particularly useful, since different GPUs have vastly different specifications, making the manual generation of GPU code an unscalable proposition.
This book serves as a valuable guide on how best to leverage parallelism to accelerate CAD algorithms. It also presents a methodology to extract automatically SIMD parallelism from regular uniprocessor code. With this approach, uniprocessor code can automatically be converted to GPU code, allowing for significant acceleration. This approach is particularly useful, since different GPUs have vastly different specifications, making the manual generation of GPU code an unscalable proposition.
Klappentext zu „Hardware Acceleration of EDA Algorithms “
Single-threaded software applications have ceased to see signi?cant gains in p- formance on a general-purpose CPU, even with further scaling in very large scale integration (VLSI) technology. This is a signi?cant problem for electronic design automation (EDA) applications, since the design complexity of VLSI integrated circuits (ICs) is continuously growing. In this research monograph, we evaluate custom ICs, ?eld-programmable gate arrays (FPGAs), and graphics processors as platforms for accelerating EDA algorithms, instead of the general-purpose sing- threaded CPU. We study applications which are used in key time-consuming steps of the VLSI design ?ow. Further, these applications also have different degrees of inherent parallelism in them. We study both control-dominated EDA applications and control plus data parallel EDA applications. We accelerate these applications on these different hardware platforms. We also present an automated approach for accelerating certain uniprocessor applications on a graphics processor. This monograph compares custom ICs, FPGAs, and graphics processing units (GPUs) as potential platforms to accelerate EDA algorithms. It also provides details of the programming model used for interfacing with the GPUs.
Inhaltsverzeichnis zu „Hardware Acceleration of EDA Algorithms “
Alternative Hardware Platforms.- Hardware Platforms.- GPU Architecture and the CUDA Programming Model.- Control Dominated Category.- Accelerating Boolean Satisfiability on a Custom IC.- Accelerating Boolean Satisfiability on an FPGA.- Accelerating Boolean Satisfiability on a Graphics Processing Unit.- Control Plus Data Parallel Applications.- Accelerating statistical static Timing Analysis Using Graphics Processors.- Accelerating Fault Simulation Using Graphics Processors.- Fault Table Generation Using Graphics Processors.- Accelerating Circuit Simulation Using Graphics Processors.- Automated Generation of GPU Code.- Automated Approach for Graphics Processor Based Software Acceleration.- Conclusions.
Bibliographische Angaben
- Autoren: Sunil P Khatri , Kanupriya Gulati
- 2010, XXII, 192 Seiten, Maße: 16,4 x 24,4 cm, Gebunden, Englisch
- Verlag: Springer, Berlin
- ISBN-10: 1441909435
- ISBN-13: 9781441909435
Sprache:
Englisch
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