Low-Power Variation-Tolerant Design in Nanometer Silicon
(Sprache: Englisch)
Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative...
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Klappentext zu „Low-Power Variation-Tolerant Design in Nanometer Silicon “
Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.
Inhaltsverzeichnis zu „Low-Power Variation-Tolerant Design in Nanometer Silicon “
Introduction and Motivation.- Background on Power Dissipation.- Background on Parameter Variations.- Low power Logic Design under Variations.- Low Power Memory Design under Variations.- System and Architecture Level Design.- Emerging Challenges and Solution Approach.- Conclusion and Discussion.
Bibliographische Angaben
- 2010, 440 Seiten, Maße: 16,3 x 24,4 cm, Gebunden, Englisch
- Herausgegeben: Swarup Bhunia, Saibal Mukhopadhyay
- Verlag: Springer, Berlin
- ISBN-10: 1441974172
- ISBN-13: 9781441974174
Sprache:
Englisch
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