Verilog and SystemVerilog Gotchas
101 Common Coding Errors and How to Avoid them
(Sprache: Englisch)
This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages.
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This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages.
Klappentext zu „Verilog and SystemVerilog Gotchas “
This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize, and avoid, these common coding mistakes. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug them.
Inhaltsverzeichnis zu „Verilog and SystemVerilog Gotchas “
Introduction, What Is A Gotcha?.- Declaration and Literal Number Gotchas.- RTL Modeling Gotchas.- Operator Gotchas.- General Programming Gotchas.- Object Oriented and Multi-Threaded Programming Gotchas.- Randomization, Coverage and Assertion Gotchas.- Tool Compatibility Gotchas.
Bibliographische Angaben
- Autoren: Stuart Sutherland , Don Mills
- 2007, 2007, 218 Seiten, Maße: 16 x 24,1 cm, Gebunden, Englisch
- Verlag: Springer
- ISBN-10: 0387717145
- ISBN-13: 9780387717142
- Erscheinungsdatum: 26.06.2007
Sprache:
Englisch
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