Verilog and SystemVerilog Gotchas (PDF)
This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog...
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This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize, and avoid, these common coding mistakes. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug them.
- Autoren: Stuart Sutherland , Don Mills
- 2010, 2007, 218 Seiten, Englisch
- Verlag: Springer-Verlag GmbH
- ISBN-10: 0387717153
- ISBN-13: 9780387717159
- Erscheinungsdatum: 30.04.2010
Abhängig von Bildschirmgröße und eingestellter Schriftgröße kann die Seitenzahl auf Ihrem Lesegerät variieren.
- Dateiformat: PDF
- Größe: 9.62 MB
- Ohne Kopierschutz
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