Approximate multipliers for image processing
By design of area and power efficiency
(Sprache: Englisch)
Approximate computing can decrease the design complexity with an increase in performance and power proficiency for error resilient applications. This brief deals with a new design approach for approximation of multipliers. The partial products of the...
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Approximate computing can decrease the design complexity with an increase in performance and power proficiency for error resilient applications. This brief deals with a new design approach for approximation of multipliers. The partial products of the multiplier are altered to introduce varying probability terms. Logic complexity of approximation is varied for the accumulation of altered partial products based on their probability. The proposed approximation is utilized in two variants of 16-bit multipliers. Synthesis results reveal that the proposed 8 bit multiplier achieve power savings and reduces the delay compared to an exact multiplier. They have better accuracy when contrasted with existing estimated multipliers. Which are better than the previous works. Performance of the proposed multipliers is evaluated with an image processing application using Gaussian filter, where Gaussian filter with proposed approximate multiplier model achieves the highest peak signal to noise ratio(PSNR).
Autoren-Porträt von Sridhar T.N.
T.N., SridharProf. Sridhar T.N., Assistant Professor, Department of Electronics and Communication Engineering, Cambridge Institute of Technology, Devanahalli, Bangalore Rural district has taught many subjects to engineering students. He has been specialised in VLSI design and Embedded system.
Bibliographische Angaben
- Autor: Sridhar T.N.
- 2021, 68 Seiten, Maße: 22 cm, Kartoniert (TB), Englisch
- Verlag: LAP Lambert Academic Publishing
- ISBN-10: 620330784X
- ISBN-13: 9786203307849
Sprache:
Englisch
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