Design of High Speed and Low Power Configurable Booth Multiplier
(Sprache: Englisch)
A configurable multiplier optimized for low power and high speed operations and which can be configured either for single 16-bit multiplication operation, single 8-bit multiplication or twin parallel 8-bit multiplication is designed. The output product can...
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A configurable multiplier optimized for low power and high speed operations and which can be configured either for single 16-bit multiplication operation, single 8-bit multiplication or twin parallel 8-bit multiplication is designed. The output product can be truncated to further decrease Power consumption and increase speed by sacrificing a bit of output precision. Furthermore, the proposed multiplier maintains an acceptable output quality with enough accuracy when truncation is performed. Thus it provides a flexible arithmetic capacity and a trade off between output precision and power consumption. The approach also dynamically detects the input range of multipliers and disables the switching operation of the non-effective ranges. Thus the ineffective circuitry can be efficiently deactivated, thereby reducing power consumption and increasing the speed of operation.
Autoren-Porträt von K. Shashidhar
Shashidhar, K.K. Shashidhar having more than 20 years of experience in the field of teaching. Completed Ph.D from GITAM University. M.Tech in VLSI System Design from JNTUH. At present working as Associate professor in the department of ECE at GNITC (Autonomous), Ibrahimpatnam, affiliated to JNTU, Hyderabad.Worked for TNTU affiliated college malaysia for 4 years.
Bibliographische Angaben
- Autor: K. Shashidhar
- 2021, 88 Seiten, Maße: 22 cm, Kartoniert (TB), Englisch
- Verlag: LAP Lambert Academic Publishing
- ISBN-10: 6204197657
- ISBN-13: 9786204197654
Sprache:
Englisch
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