Field-Programmable Logic and Applications, FPL 1997

Multicontext dynamic reconfiguration and real-time probing on a novel mixed signal programmable device with on-chip microprocessor.- CAD-oriented FPGA and dedicated CAD system for telecommunications.- Rothko: A three dimensional FPGA architecture, its fabrication, and design tools.- Extending dynamic circuit switching to meet the challenges of new FPGA architectures.- Performance evaluation of a full speed PCI initiator and target subsystem using FPGAs.- Implementation of pipelined multipliers on Xilinx FPGAs.- The XC620ODS development system.- Thermal monitoring on FPGAs using ring-oscillators.- A reconfigurable approach to low cost media processing.- Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research.- Stream synthesis for a wormhole run-time reconfigurable platform.- Pipeline morphing and virtual pipelines.- Parallel graph colouring using FPGAs.- Run-time compaction of FPGA designs.- Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement.- A case study of partially evaluated hardware circuits: Key-specific DES.- Run-time parameterised circuits for the Xilinx XC6200.- Automatic identification of swappable logic units in XC6200 circuitry.- Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic.- Exploiting reconfigurability through domain-specific systems.- Technology mapping by binate covering.- VPR: a new packing, placement and routing tool for FPGA research.- Technology mapping of heterogeneous LUT-based FPGAs.- Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs.- Technology mapping of LUT based FPGAs for delay optimisation.- Automatic Mapping of Algorithms onto multiple FPGA-SRAM Modules.- FPLD HDL synthesis employing high-level evolutionary algorithm optimisation.- An hardware/software partitioning algorithm for custom computing machines.- The Java