Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Voltage.- Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing.- Back Annotation in High Speed Asynchronous Design.- Session 6: System-on-Chip Design.- Optimization of Reliability and Power Consumption in Systems on a Chip.- Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs.- A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design.- Power Supply Selective Mapping for Accurate Timing Analysis.- Session 7: Busses and Interconnections.- Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses.- PSK Signalling on NoC Buses.- Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding.- Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing.- Efficient Simulation of Power/Ground Networks with Package and Vias.- Session 8: Modeling.- Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation.- Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates.- Compact Static Power Model of Complex CMOS Gates.- Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model.- Statistical Critical Path Analysis Considering Correlations.- Session 9: Design Automation.- A CAD Platform for Sensor Interfaces in Low-Power Applications.- An Integrated Environment for Embedded Hard Real-Time Systems Scheduling with Timing and Energy Constraints.- Efficient Post-layout Power-Delay Curve Generation.- Power - Performance Optimization for Custom Digital Circuits.- Switching-Activity Directed Clustering Algorithm for Low Net-Power Implementation of FPGAs.- Session 10: Low-Power Techniques.- Logic-Level Fast Current Simulation for Digital CMOS Circuits.- Design of Variable Input Delay Gates for Low Dynamic Power Circuits.- Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications.- Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes.- Session 11: Memory and Register Files.- Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs.- Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs.- Static Noise Margin Analysis of Sub-threshold SRAM Cells in Deep Sub-micron Technology.- An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder Buffers.- Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers.- Poster Session 1: Applications.- Low-Power Aspects of Nonlinear Signal Processing.- Reducing Energy Consumption of Computer Display by Camera-Based User Monitoring.- Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives.- A Design Methodology for Secured ICs Using Dynamic Current Mode Logic.- Power Consumption Characterisation of the Texas Instruments TMS320VC5510 DSP.- A Method to Design Compact Dual-rail Asynchronous Primitives.- Enhanced GALS Techniques for Datapath Applications.- Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling Study.- Poster Session 2: Digital Circuits.- Area-Aware Pipeline Gating for Embedded Processors.- Fast Low-Power 64-Bit Modular Hybrid Adder.- Speed Indicators for Circuit Optimization.- Synthesis of Hybrid CBL/CMOS Cell Using Multiobjective Evolutionary Algorithms.- Power-Clock Gating in Adiabatic Logic Circuits.- The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics.- Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers.- Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures.- Poster Session 3: Analog and Physical Design.- The Optimal Wire Order for Low Power CMOS.- Effect of Post-oxidation Annealing on the Electrical Properties of Anodic Oxidized Films in Pure Water.- Temperature Dependency in UDSM Process.- Circuit Design Techniques for On-Chip Power Supply Noise Monitoring System.- A Novel Approach to the Design of a Linearized Widely Tunable Very Low Power and Low Noise Differential Transconductor.- A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers.- Special Session: Digital Hearing Aids: Challenges and Solutions for Ultra Low Power.- Digital Hearing Aids: Challenges and Solutions for Ultra Low Power.- Tutorial Hearing Aid Algorithms.- Optimization of Digital Audio Processing Algorithms Suitable for Hearing Aids.- Optimization of Modules for Digital Audio Processing.- Invited Talks.- Traveling the Wild Frontier of Ultra Low-Power Design.- DLV (Deep Low Voltage): Circuits and Devices.- Wireless Sensor Networks: A New Life Paradigm.- Cryptography: Circuits and Systems Approach.