Logic and Architecture Synthesis

Introduction. Logic minimization based on BDD. Boolean Optimisation using implicit techniques. Multi level logic optimization with boolean relations. BONSAI: A pragmatic approach to logic synthesis and formal verification. Cell assignment based on BDD. Combined approach of BDDs structural analysis in the mapping and matching of logic functions. Efficient ROBDD based computation of common decomposition functions of multi-output boolean functions. Circuit depth optimisation by BDD-based function decomposition. Symmetry based variable ordering for ROBBD. Partitioning and clustering for programmable devices. Circuit clustering and partitioning for system implementation. Circuit partitioning for FPGA. Logic synthesis for programmable devices. Balanced multilevel decomposition and its applications in FPGA based synthesis. Disjoint decomposition for LUT FPGA technology. Performance comparison of programmable logic blocks families using macro cells generators. Structural optimization. Area optimization of bit-parallel custom data paths. Data path regularity extraction. NEPR a synthesis tool for speed optimization. Controllers. ROM based multi thread controller. State assignment selection for CPLD and FPGA. Control optimization and hardware translation of Esterel. SEC state assignment selection: consequences on the area and reliability of fault tolerant controllers. On multi-cycle false paths in sequential circuits. Control part and operative part. Low power VLSI design method for data path and controllers. Behavioural synthesis control scheme in question. Link to libraries. RAM based architectural synthesis. Module generators and their integration in an architectural synthesis system. Towards better accounting of physical design effects in high level synthesis. Operator type selection. Delay area trade-off exploration using an architectural jiggling algorithm. Influence of modern computer arithmetic on synthesis. Adder synthesis. High level synthesis. High level synthesis: