Processing-in-Memory for AI (PDF)

Computer Engineering (ECE) at University of California, Santa Barbara.

From 2006 to 2010, he was with System LSI, Samsung Electronics, Yongin, South Korea. In 2012, he joined Wireless Business, Texas Instruments, Dallas, TX, USA as a SRC Summer Intern. He also joined Mixed-Signal Communication IC Design Group, IBM T.J. Watson Research Center as a Research Summer Intern in 2013. He was an Engineering Intern and a senior technical staff in Memory and Interface Division, Rambus Inc., Sunnyvale, CA, USA, from 2014 to 2016. Prof. Kim is the recipient of a Doctoral Dissertation Fellowship Award, a ISLPED Low Power Design Contest Award and an Intel/IBM/Catalyst Foundation CICC Student Award. His research works appeared in top circuit conferences and journals including ISSCC, VLSI symposium, CICC and JSSC. His current research focuses on memory-centric computing circuits/architecture using embedded memories for artificial intelligence, machine learning, and alternative computing solutions for solving combinatorial optimization problems.

Tony Tae-Hyoung Kim received the B.S. and M.S. degrees in electrical engineering from Korea University, Seoul, Korea, in 1999 and 2001, respectively. He received the Ph.D. degree in electrical and computer engineering from the University of Minnesota, Minneapolis, MN, USA in 2009. From 2001 to 2005, he worked for Samsung Electronics where he performed research on the design of high-speed SRAM memories, clock generators, and IO interface circuits. In 2007 ~ 2009 summer, he was with IBM T. J. Watson Research Center and Broadcom Corporation where he performed research on isolated NBTI/PBTI measurement circuits and SRAM mismatch measurement test structure, and battery backed memory design, respectively. In November 2009, he joined Nanyang Technological University where he is currently an associate professor. His current research interests include low power and high performance digital, mixed-mode, and memory circuit design, ultra-low voltage sub-threshold circuit design for energy efficiency, variation and aging tolerant circuits and systems, approximate computing, and circuit techniques for 3D ICs.

He received Best Demo Award at 2016 IEEE APCCAS, International Low Power Design Contest award at 2016 IEEE/ACM ISLPED, a best paper award at 2014 and 2011 ISOCC, 2008 AMD/CICC Student Scholarship Award, 2008 Departmental Research Fellowship from U. of Minnesota, 2008 IEEE DAC/ISSCC Student Design Contest Award, 2008 Samsung Humantec Thesis Award (Bronze Prize), 2005 ETRI Journal Paper of the Year Award, 2001 Samsung Humantec Thesis Award (Honor Prize), and 1999 Samsung Humantec Thesis Award (Silver Prize). He is an author/co-author of +160 journal and conference papers and holds 17 US and Korean patents. He serves as an Associate Editor of IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Access, and IEIE Journal of Semiconductor Technology and Science (JSTS). He has also served as a technical committee member of various conferences such as IEEE Asian Solid-State Circuits Conference (A-SSCC), IEEE International Symposium on Circuits and Systems (ISCAS), IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), etc. He was the Chair of IEEE SSCS Singapore Chapter in 2015~2016. He is a senior member of IEEE.