Analysis and VLSI Architecture of High Definition and Scalable VideoCoding Standards
(Sprache: Englisch)
This book details algorithm analysis and VLSI architecture of video encoders, especially for high definition and scalable video coder. It examines the three design challenges and related system issues of memory bandwidth , hardware area and power consumption.
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This book details algorithm analysis and VLSI architecture of video encoders, especially for high definition and scalable video coder. It examines the three design challenges and related system issues of memory bandwidth , hardware area and power consumption.
Klappentext zu „Analysis and VLSI Architecture of High Definition and Scalable VideoCoding Standards “
This book addresses the algorithm analysis and VLSI architecture of video encoders, especially for high definition and scalable video coder. The three design challenges and related system issues of memory bandwidth (including system memory and internal memory), hardware area, and power consumption (required operating frequency) are all discussed. With the high definition encoder, the authors focus on algorithm modification and design parallelism to provide high processing capability for the video encoder. Several corresponding hardware schedules are also included to cooperate with proposed architecture. For scalable video coding, the emphasis is placed not only on video algorithms, but also on hardware performance. The algorithm modification, data reuse schemes from frame-level to candidates-level, and architecture design contribute in the developing of three scalabilities and first MCTF hardware design. Finally, the first SVC encoder chip for HDTV1080p is presented and all abovedesign issues are considered together.
This book addresses the algorithm analysis and VLSI architecture of video encoders, especially for high definition and scalable video coder. The three design challenges and related system issues of memory bandwidth (including system memory and internal memory), hardware area, and power consumption (required operating frequency) are all discussed. With the high definition encoder, the authors focus on algorithm modification and design parallelism to provide high processing capability for the video encoder. Several corresponding hardware schedules are also included to cooperate with proposed architecture. For scalable video coding, the emphasis is placed not only on video algorithms, but also on hardware performance. The algorithm modification, data reuse schemes from frame-level to candidates-level, and architecture design contribute in the developing of three scalabilities and first MCTF hardware design. Finally, the first SVC encoder chip for HDTV1080p is presented and all above design issues are considered together.
Inhaltsverzeichnis zu „Analysis and VLSI Architecture of High Definition and Scalable VideoCoding Standards “
Part I: High Definition Video Encoder.- Frame-Parallel Design Strategy for High Definition Video Encoder with B-frame.- Algorithm and Architecture Design for Intra Prediction in H.264/AVC High Profile.- Part II: Scalable Video Coding.- Fast Prediction Algorithm of Adaptive GOP Structure for SVC.- Efficient Architecture Design of Motion.-.Compensated Temporal Filtering/Motion Compensated Prediction Engine.- Cost-Efficient Residual Prediction VLSI Architecture for H.264/AVC Scalable Extension.- Architecture Design of Fine Grain SNR Scalable Encoder with CABAC for H.264/AVC Scalable Extension.- Part III: HDTV1080p H.264/AVC High Profile and Scalable Extension Encoder Chip.- An H.264/AVC Scalable Extension and High Profile HDTV 1080p Encoder Chip.- Conclusion.
Bibliographische Angaben
- Autoren: Liang-Gee Chen , Yi-Hau Chen
- 2011, 250 Seiten, Maße: 15,5 x 23,5 cm, Gebunden, Englisch
- Verlag: Springer
- ISBN-10: 1441961445
- ISBN-13: 9781441961440
Sprache:
Englisch
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