Analysis & Implementation of FlipFlop Grouping with Clock Gating
(Sprache: Englisch)
The memory circuit has sequential elements as flip-flops, registers which are being used for storing and transferring data. The memory stores the data with the help of the clock signal in the flip-flops. The flip-flops are the edge triggered device which...
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The memory circuit has sequential elements as flip-flops, registers which are being used for storing and transferring data. The memory stores the data with the help of the clock signal in the flip-flops. The flip-flops are the edge triggered device which can be enabled either by a positive or negative clock cycle, so the complementary cycle either the negative or positive will be left without processing which creates a need for large number of clock pulse which in turn increases the power consumption. Thus flip- flops are proposed to act on both the clock cycles. The flip-flops are 1-bit element so they are grouped together to store multiple bits based on the flip-flop grouping technique which reduces the number of clock pulse. The Clock Gating technique overcomes the power consumption occurring when the system is active on unnecessary period of time by tuning the system into ideal mode.
Autoren-Porträt von Arthi Rangaraj, Subhashini Uvaraj
Rangaraj, ArthiArthi Rangaraj and Subhashini Uvaraj are working as Assistant Professor in Department of Electronics and Communication Engineering in KIT-KalaignarKarunanidhi Institute of Technology, Coimbatore,India. They have completed their Master's (VLSI Design) and Bachelor's degree(ECE). They are members of various professional bodies like ISRD, ISTE & IAENG
Bibliographische Angaben
- Autoren: Arthi Rangaraj , Subhashini Uvaraj
- 2020, 88 Seiten, Maße: 22 cm, Kartoniert (TB), Englisch
- Verlag: LAP Lambert Academic Publishing
- ISBN-10: 6200265682
- ISBN-13: 9786200265685
Sprache:
Englisch
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