Design of Prefix Adders Using Transmission Gate
(Sprache: Englisch)
The design of 64-bit parallel prefix adder using transmission gate which acquires least number of nodes with the lowest transistor count and low power consumption has been addressed in this book. The 64-bit parallel prefix adder is designed and comparison...
Leider schon ausverkauft
versandkostenfrei
Buch
35.90 €
17 DeutschlandCard Punkte
sammeln
- Lastschrift, Kreditkarte, Paypal, Rechnung
- Kostenlose Rücksendung
Produktdetails
Produktinformationen zu „Design of Prefix Adders Using Transmission Gate “
Klappentext zu „Design of Prefix Adders Using Transmission Gate “
The design of 64-bit parallel prefix adder using transmission gate which acquires least number of nodes with the lowest transistor count and low power consumption has been addressed in this book. The 64-bit parallel prefix adder is designed and comparison is made among previous parallel prefix adders. The result shows that the proposed 64-bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the speed. The proposed parallel prefix adders consumes less power and implements lesser number of transistors compared to existing parallel prefix adders.
Bibliographische Angaben
- Autoren: Nehru Kandasamy , Nagarjuna Telagam
- 2017, 52 Seiten, Maße: 22 cm, Kartoniert (TB), Englisch
- Verlag: LAP Lambert Academic Publishing
- ISBN-10: 6202079932
- ISBN-13: 9786202079938
Sprache:
Englisch
Kommentar zu "Design of Prefix Adders Using Transmission Gate"
0 Gebrauchte Artikel zu „Design of Prefix Adders Using Transmission Gate“
| Zustand | Preis | Porto | Zahlung | Verkäufer | Rating |
|---|
Schreiben Sie einen Kommentar zu "Design of Prefix Adders Using Transmission Gate".
Kommentar verfassen