Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs
(Sprache: Englisch)
The models and procedures for designing pipeline analog-to-digital converters presented here compensate for device inaccuracies, enabling high-performance specifications which can be met within brief design cycles with significantly fewer model iterations.
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The models and procedures for designing pipeline analog-to-digital converters presented here compensate for device inaccuracies, enabling high-performance specifications which can be met within brief design cycles with significantly fewer model iterations.
Klappentext zu „Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs “
This book presents models and procedures to design pipeline analog-to-digital converters, compensating for device inaccuracies, so that high-performance specs can be met within short design cycles. These models are capable of capturing and predicting the behavior of pipeline data converters within less than half-a-bit deviation, versus transistor-level simulations. As a result, far fewer model iterations are required across the design cycle. Models described in this book accurately predict transient behaviors, which are key to the performance of discrete-time systems and hence to the performance of pipeline data converters.
Inhaltsverzeichnis zu „Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs “
- Pipeline ADC Overview- Design Methodologies for Pipeline ADCs
- Pipeline ADC Electrical-level Synthesis Tool
- Behavioural Modeling of Pipeline ADCs
- Case Study: Design of a 10BIT@60MS Pipeline ADC
- Experimental Results and State of the Art
- Conclusions and Future Lines of Research
Bibliographische Angaben
- Autoren: Jesús Ruiz-Amaya , Manuel Delgado-Restituto , Ángel Rodríguez-Vázquez
- 2011, 2011, XIII, 209 Seiten, Maße: 23,5 x 23,4 cm, Kartoniert (TB), Englisch
- Verlag: Springer, Berlin
- ISBN-10: 1489993185
- ISBN-13: 9781489993182
Sprache:
Englisch
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