Digital Communications Test and Measurement: High-Speed Physical Layer Characterization

the Oscilloscope 330 7.3 Oscilloscope Bandwidth and Sample Rate 331 7.4 Waveform Acquisition Process for the Sampling Oscilloscope 335 7.5 Sources of Instrumentation Noise 346 7.6 Parametric Analysis of Waveforms 350 7.7 The Effect of Oscilloscope Bandwidth on Waveform Results 353 7.8 Measurements of the Eye Diagram 358 7.9 Return-to-Zero Signals 382 7.10 Advanced Jitter Analysis 387 7.11 Summary 417 7.12 References 418 Chapter 8 High-Speed Waveform Analysis Using All-Optical Sampling 421 8.1 Introduction 422 8.2 Principles of Optical Sampling 427 8.3 Performance Measures of All-Optical Sampling Systems 441 8.4 Timebase Designs 464 8.5 Experimental Implementation and Key Building Blocks 475 8.6 Related Applications and Possible Future Directions 492 8.7 Summary 498 8.8 References 499 Chapter 9 Clock Synthesis, Phase Locked Loops, and Clock Recovery 505 9.1 Oscillators and Phase Noise 506 9.2 Phase Locked Loops and Clock Synthesis 510 9.3 Clock Data Recovery Circuits 512 9.4 PLL and Clock Recovery Dynamic Behavior 517 9.5 Measuring PLL Dynamics 523 9.6 Measuring Phase Noise and Jitter Spectrum 525 9.7 Summary 531 9.8 References 532 Chapter 10 Jitter Tolerance Testing 533 10.1 Introduction 533 10.2 Jitter Tolerance: Basic Measurement Method and Test Setup 536 10.3 Generation of Jitter Tolerance Test Signals 539 10.4 Jitter Tolerance Measurement Method and Test Setup 555 10.5 Summary 560 10.6 References 560 Chapter 11 Sensitivity Testing in Optical Digital Communications 563 11.1 Introduction: Optical Digital Receivers 564 11.2 The Basics of Optical Sensitivity Measurements 565 11.3 BER Calculations in Real Communications Systems 588 11.4 Summary 602 11.5 References 603 Chapter 12 Stress Tests in High-Speed Serial Links 605 12.1 The Need for High-Speed Serial Communication 606 12.2 Early High-Speed Optical Stressed-Eye Tests 607 12.3 BER versus OSNR 609 12.4 10 Gigabit Ethernet: IEEE 802.3ae 618 12.5 The Advent of Electronic Dispersion Compensation 629 12.6 LRM Stress Testing (IEEE 802.3aq) 634 12.7 Future Standards 641 12.8 Summary 654 12.9 References 655 Chapter 13 Measurements on Interconnects 657 13.1 Measurements and Characterization of Interconnects 658 13.2 Modeling of System Performance from Measurements 689 13.3 Summary 709 13.4 References 710 Chapter 14 Frequency Domain Measurements 713 14.1 Introduction 714 14.2 Understanding Network Analyzer Hardware 716 14.3 Understanding S-Parameters 729 14.4 Error Correction and Calibration Methods 740 14.5 Graphical Representations 749 14.6 Example Devices 758 14.7 Summary 783 14.8 References 783 Chapter 15 Jitter and Signaling Testing for Chip-to-Chip Link Components and Systems 785 15.1 Introduction 785 15.2 Multiple Gigabit per Second Computer Chip-to-Chip I/O Link Architectures 788 15.3 Chip-to-Chip Link System BER and Signaling Tests 800 15.4 Testing Examples 811 15.5 Future Technology Trends for High-Speed Links 815 15.6 Summary 817 15.7 References 817 Appendix A Pseudo-Random Binary Sequences 819Appendix B Passive Elements for Test Setups 835 Appendix C Coaxial Cables and Connectors 847Appendix D Supplemental Materials for Chapter 3 861 Index 911