Digital Systems Design and Prototyping
Using Field Programmable Logic and Hardware Description Languages
(Sprache: Englisch)
Digital Systems Design and Prototyping: Using Field Programmable Logic and Hardware Description Languages, Second Edition covers the subject of digital systems design using two important technologies: Field Programmable Logic Devices (FPLDs) and Hardware...
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Digital Systems Design and Prototyping: Using Field Programmable Logic and Hardware Description Languages, Second Edition covers the subject of digital systems design using two important technologies: Field Programmable Logic Devices (FPLDs) and Hardware Description Languages (HDLs). These two technologies are combined to aid in the design, prototyping, and implementation of a whole range of digital systems from very simple ones replacing traditional glue logic to very complex ones customized as the applications require. Three HDLs are presented: VHDL and Verilog, the widely used standard languages, and the proprietary Altera HDL (AHDL). The chapters on these languages serve as tutorials and comparisons are made that show the strengths and weaknesses of each language.
A large number of examples are used in the description of each language providing insight for the design and implementation of FPLDs.
With the addition of the Altera UP-1 prototyping board, all examples can be tested and verified in a real FPLD.
Digital Systems Design and Prototyping: Using Field Programmable Logic and Hardware Description Languages, Second Edition is designed as an advanced level textbook as well as a reference for the professional engineer.
Inhaltsverzeichnis zu „Digital Systems Design and Prototyping “
to Field Programmable Logic Devices.- Examples of Major FPLD Families.- Design Tools and Logic Design with FPLDS.- to Design Using AHDL.- Advanced AHDL.- Design Examples.- Simp-Asimplecustomizable Microprocessor.- Rapid Prototyping Using FPLDS - Vuman Case Study.- to VHDL.- Objects, Data Types and Processes.- VHDL and Logic Synthesis.- Example Designs and Problems.- to Verilog HDL.- Verilog and Logic Synthesis by Examples.- A Verilog Example: Pipelined Simp.
Bibliographische Angaben
- Autoren: Zoran Salcic , Asim Smailagic
- 2013, 2. Aufl., XXI, 621 Seiten, Maße: 15,5 x 23,5 cm, Kartoniert (TB), Englisch
- Verlag: Springer, Berlin
- ISBN-10: 1475784198
- ISBN-13: 9781475784190
Sprache:
Englisch
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