Electronic Chips & Systems Design Languages
(Sprache: Englisch)
Electronic Chips & Systems Design Languagesoutlines and describes the latest advances in design languages. The challenge of System on a Chip (SOC) design requires designers to work in a multi-lingual environment which is becoming increasingly difficult...
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Electronic Chips & Systems Design Languagesoutlines and describes the latest advances in design languages. The challenge of System on a Chip (SOC) design requires designers to work in a multi-lingual environment which is becoming increasingly difficult to master. It is therefore crucial for them to learn, almost in real time, from the experiences of their colleagues in the use of design languages and how these languages have become more advanced to cope with system design. System designers, as well as students willing to become system designers, often do not have the time to attend all scientific events where they could learn the necessary information. This book will bring them a selected digest of the best contributions and industry strength case studies. All the levels of abstraction that are relevant, from the informal user requirements down to the implementation specifications, are addressed by different contributors. The author, together with colleague authors who provide valuable additional experience, presents examples of actual industrial world applications. Furthermore the academic concepts presented in this book provide excellent theories to student readers and the concepts described are up to date and in so doing provide most suitable root information for Ph.D. postgraduates.
Inhaltsverzeichnis zu „Electronic Chips & Systems Design Languages “
Contributors. Preface. VHDL Extensions.
I: VHDL-AMS - Introduction; A. Vachoux.
1. Library Development Using the VHDL-AMS Language; E. Christen, K. Bakalar.
2. Behavioral Modeling of Complex Heterogeneous Microsystems; P. Schwarz, J. Haase.
3. VHDL-AMS, a Unified Language to Describe Multi-Domain, Mixed-Signals Designs. Mechatronic Applications; V. Aubert, S. Garcia-Sabiro.
4. Efficient Modeling of Analog and Mixed A/D Systems via Piece-Wise Linear Technique; J. Dabrowski, A. Pulka.
II: OO-VHDL.
5. SUAVE: Object-Oriented and Genericity Extensions to VHDL for High-Level Modeling; P. Ashenden, et al.
6. Digital Circuit Design with Objective VHDL; M. Radetzki, W. Nebel.
System Level Design.
I: HW/SW Co-design.
7. UF: Architecture and Semantics for System-Level Multiformalism Descriptions; L.S. Fernandez, et al.
8. Automatic Interface Generation among VHDL Processes in HW/SW Co-Design; E. Barros, C. de Araujo.
9. System-Level Specification and Architecture Exploration: An Avionics Codesign Application; F. Clouté, et al.
10. Using SDL to Model Reactive Embedded System in a Co-design Environment; R. Kumar.
11. A Synchronous Object-Oriented Design Flow for Embedded Applications; P.G. Plöger, et al.
II: Co-simulation.
12. Heterogeneous System-Level Cosimulation with SDL and Matlab; P. Bjuréus, A. Jantsch.
13. VHDL-Based HW/SW Cosimulation of Microsystems; V. Moser, et al.
14. Modeling Interrupts for HW/SW Co-Simulation Based on VHDL/C Coupling; M. Bauer, et al.
III: SLD methodology.
15. A Comparison of Six Languages for System Level Description of Telecom Applications; A. Jantsch, et al.
16. High Level Modelling in SDL and VHDL+; F. Cook, et al.
17. ECL: A Specification Environment for System-Level Design; E. Sentovich, et al.
18. The MCSE Approach for System-Level Design; J.P. Calvez, et al. Synthesis.
19. Automatic VHDL Restructuring for RTL Synthesis Optimization and Testability Improvement; D. Sciuto, et al.
20. VHDL
... mehr
Dynamic Loop Synthesis; M.F. Albenge, D. Houzet.
21. Hierarchical Module Expansion in a VHDL Behavioural Synthesis System; A.D. Brown, et al.
Formal Verification.
I: Formal Verification.
22. Port-Stitching: An Interface-Oriented Hardware Specification and VHDL Model Generation; A.F. Nicolae, E. Cerny.
23. Formal Verification of VHDL using VHDL-Like ACL2 Models; D. Borrione, P. Georgelin.
24. Specification of Embedded Monitors for Property Checking; M. Bombana, et al.
25. Formal Specification and Verification of Transfer-Protocols for System-Design in VHDL; O. Drögehorn, et al.
21. Hierarchical Module Expansion in a VHDL Behavioural Synthesis System; A.D. Brown, et al.
Formal Verification.
I: Formal Verification.
22. Port-Stitching: An Interface-Oriented Hardware Specification and VHDL Model Generation; A.F. Nicolae, E. Cerny.
23. Formal Verification of VHDL using VHDL-Like ACL2 Models; D. Borrione, P. Georgelin.
24. Specification of Embedded Monitors for Property Checking; M. Bombana, et al.
25. Formal Specification and Verification of Transfer-Protocols for System-Design in VHDL; O. Drögehorn, et al.
... weniger
Bibliographische Angaben
- 2010, X, 306 Seiten, Maße: 15,5 x 23,7 cm, Kartoniert (TB), Englisch
- Herausgegeben: Jean Mermet
- Verlag: Springer, Berlin
- ISBN-10: 1441948848
- ISBN-13: 9781441948847
Sprache:
Englisch
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