Guide to RISC Processors
for Programmers and Engineers
(Sprache: Englisch)
Details RISC design principles as well as explains the differences between this and other designs.Helps readers acquire hands-on assembly language programming experience
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Details RISC design principles as well as explains the differences between this and other designs.Helps readers acquire hands-on assembly language programming experience
Klappentext zu „Guide to RISC Processors “
Details RISC design principles as well as explains the differences between this and other designs.Helps readers acquire hands-on assembly language programming experience
Inhaltsverzeichnis zu „Guide to RISC Processors “
Part I--OVERVIEW: Introduction * Processor design issues * RISC principles Part II--ARCHITECTURES: MIPS architecture * SPARC architecture * PowerPC architecture * Itanium architecture * ARM architecture Part III--MIPS ASSEMBLY LANGUAGE: SPIM simulator and debugger * Assembly language overview * Procedures and the stack * Addressing modes * Arithmetic instructions * Conditional execution * Logical and shift operations * Recursion * Floating-point operations Appendixes: Number Systems * Character Representation * MIPS Instruction Set Summary * Programming Exercises Bibliography * Index
Autoren-Porträt von Sivarama P. Dandamudi
Here is an accessible, comprehensive guide to all the popular modern RISC (Reduced Instruction Set Computer) processors: MIPS, SPARC, PowerPC, ARM and Itanium. It details RISC design principles as well as explains the differences between RISC and CISC designs. It also covers MIPS assembly language programming. Professionals and programmers seeking an authoritative and practical overview of RISC processors will find the guide an essential resource.
Bibliographische Angaben
- Autor: Sivarama P. Dandamudi
- 2010, Softcover reprint of hardcover 1st ed. 2005, 388 Seiten, Maße: 17,5 x 25,4 cm, Kartoniert (TB), Englisch
- Verlag: Springer, Berlin
- ISBN-10: 144191935X
- ISBN-13: 9781441919359
Sprache:
Englisch
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