Handbook of 3D Integration.Vol.1/2
Technology and Applications of 3D Integrated Circuits
(Sprache: Englisch)
With contributions from key players in both academia and industry, this first encompassing treatise of this important field puts the known physical limitations for classic 2D electronics into perspective with the need for further electronics developments and market necessities.
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With contributions from key players in both academia and industry, this first encompassing treatise of this important field puts the known physical limitations for classic 2D electronics into perspective with the need for further electronics developments and market necessities.
Klappentext zu „Handbook of 3D Integration.Vol.1/2 “
The first encompassing treatise of this new and very important field puts the known physical limitations for classic 2D microelectronicsinto perspective with the requirements for further microelectronics developments and market necessities. This two-volume handbookpresents 3D solutions to the feature density problem, addressing all important issues, such as wafer processing, die bonding, packagingtechnology, and thermal aspects. It begins with an introductory part, which defines necessary goals, existing issues and relates 3D integrationto the semiconductor roadmap of the industry. Before going on to cover processing technology and 3D structure fabrication strategies indetail. This is followed by fields of application and a look at the future of 3D integration.The editors have assembled contributions from key academic and industrial players in the field, including Intel, Micron, IBM, Infineon,Qimonda, NXP, Philips, Toshiba, Semitool, EVG, Tezzaron, Lincoln Labs, Fraunhofer, RPI, IMEC, CEA-LETI and many others.
Inhaltsverzeichnis zu „Handbook of 3D Integration.Vol.1/2 “
Volume 1PREFACEINTRODUCTION TO 3D INTEGRATIONIntroductionHistorical Evolution of Stacked Wafer Concepts3D Packaging vs 3D IntegrationNon-TSV 3D Stacking TechnologiesDRIVERS FOR 3D INTEGRATIONIntroductionElectrical PerformancePower Consumption and NoiseForm FactorLower CostApplication Based DriversOVERVIEW OF 3D INTEGRATION PROCESS TECHNOLOGY3D Integration TerminologyProcessing SequencesTechnologies for 3D IntegrationPART I: Through Silicon Via FabricationDEEP REACTIVE ION ETCHING OF THROUGH SILICON VIASIntroductionDRIE Equipment and CharacterizationDRIE ProcessingPractical Solutions in Via EtchingConcluding RemarksLASER ABLATIONIntroductionLaser Technology for 3D PackagingFor Si SubstrateResults for 3D Chip StackingReliabilitiesThe FutureSIO2IntroductionDielectric CVDDielectric Film Properties3D-Specifics Regarding SiO2 DielectricsConcluding RemarksINSULATION - ORGANIC DIELECTRICSParylenePlasma-Polymerized BCBSpray-Coated Organic InsulatorsLaser-Drilled OrganicsConcluding RemarksCOPPER PLATINGIntroductionCopper Plating EquipmentCopper Plating ProcessesFactors Affecting Copper PlatingPlating ChemistriesPlating Process RequirementsSummaryMETALLIZATION BY CHEMICAL VAPOR DEPOSITION OF W AND CUIntroductionCommercial PrecursorsDeposition Process FlowComplete TSV Metallization Including Filling and Etchback/CMPConclusionsPART II: Wafer Thinning and Bonding TechnologyFABRICATION, PROCESSING AND SINGULATION OF THIN WAFERSApplications for Thin Silicon DiesPrincipal Facts: Thinning and Wafer BowGrinding and ThinningStability and FlexibilityChip Thickness, Theoretical Model, Macroscopic FeaturesStabilizing the Thin Wafer: Tapes and Carrier SystemsSeparating the Chips: Dicing Influencing the StabilityConclusionsSummaryOVERVIEW OF BONDING TECHNOLOGIES FOR 3D INTEGRATIONIntroductionDirect BondingAdhesive and Solder BondingComparison of the Different Bonding TechnologiesCHIP-TO-WAFER AND WAFER-TO-WAFER INTEGRATION SCHEMESDecision Criteria for 3D IntegrationEnabling
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TechnologiesIntegration Schemes for 3D InterconnectConclusionPOLYMER ADHESIVE BONDING TECHNOLOGYPolymer Adhesive Bonding PrinciplePolymer Adhesive Bonding Requirements and MaterialsWafer Bonding Technology Using Polymer AdhesivesBonding CharacterizationsConclusionsBONDING WITH INTERMETALLIC COMPOUNDSIntroductionTechnological ConceptsConclusionVolume 2PART III: Integration ProcessesCOMMERCIAL ACTIVITYIntroductionChip-on-Chip ActivityImaging Chips with TSVMemoryMicroprocessors & Misc. ApplicationsWAFER-LEVEL 3D SYSTEM INTEGRATIONIntroductionWafer-Level 3D System Integration TechnologiesReliability IssuesConclusionsINTERCONNECT PROCESS AT THE UNIVERSITY OF ARKANSASIntroductionTSV Process FlowChip AssemblySystem IntegrationSummaryVERTICAL INTERCONNECTION BY ASETIntroductionFabrication Process Overview Via Filling by Cu ElectrodepositionHandling of Thin Wafer3D Chip StackingThermal Performance of Chip Stack ModuleElectric Performance of Vertical InterconnectionPractical Application of Through-viasConclusion3D INTEGRATION AT CEA-LETIIntroductionCircuit Transfer for Efficient Stacking in 3D IntegrationNon-Destructive Characterization of Stacked LayersExample of 3D Integration Application DevelopmentsSummaryLINCOLN LABORATORY.S 3D CIRCUIT INTEGRATION TECHNOLOGYIntroductionLincoln Laboratory.s Wafer-Scale 3D Circuit Integration TechnologyTransferred FDSOI Transistor and Device Properties3D Circuit and Device ResultsSummary3D INTEGRATION TECHNOLOGIES AT IMECIntroduction 413Key Requirements for 3D-Interconnect Technologies3D Technologies at IMECFABRICATION USING COPPER THERMO-COMPRESSION BONDING AT MITIntroductionCopper Thermo-Compression BondingProcess FlowDiscussionSummaryRENSSELAER 3D INTEGRATION PROCESSESIntroductionVia-Last 3D Platform Using Adhesive Wafer Bonding and Cu Damascene Inter-Wafer InterconnectVia-Last 3D Platform Feasibility Demonstration: Via-Chain Structure with Key Unit Processes of Alignment, Bonding, Thinning andInter-wafer InterconnectionVia-First 3D Platform with Wafer-Bonding of Damascene-Patterned Metal/Adhesive Redistribution LayersVia-First 3D Platform Feasibility Demonstration: Via-Chain Structure with Cu/BCB Redistribution LayersUnit Process AdvancementsCarbon Nanotube (CNT) InterconnectSummary3D INTEGRATION AT TEZZARON SEMICONDUCTOR CORPORATIONIntroductionCopper BondingYield IssuesInterconnect DensityProcess Requirements for 3D DRAMFaStack Process OverviewBonding Before ThinningTezzaron.s TSVsStacking Process Flow Details (with SuperContacts)Stacking Process Flow with SuperViasAdditional Stacking Process IssuesWorking 3D DevicesQualification ResultsFaStack SummaryAbbreviations and Definitions3D INTEGRATION AT ZIPTRONIX, INC.IntroductionDirect BondingDirect Bond InterconnectProcess Cost and Supply Chain Considerations3D INTEGRATION ZYCUBEIntroductionCurrent 3D-LSI - New CSP Device for SensorsFuture 3D-LSI TechnologyPART IV: Design, Performance, and Thermal ManagementDESIGN FOR 3D INTEGRATION AT NORTH CAROLINA STATE UNIVERSITYWhy 3D?Interconnect-Driven Case StudiesComputer-Aided DesignDiscussionMODELING APPROACHES AND DESIGN METHODS FOR 3D SYSTEM DESIGNIntroductionModeling and SimulationDesign Methods for 3D IntegrationConclusionsMULTIPROJECT CIRCUIT DESIGN AND LAYOUT IN LINCOLN LABORATORY.S 3D TECHNOLOGYIntroduction3D Design and Layout PracticeDesign and Submission ProceduresCOMPUTER-AIDED DESIGN FOR 3D CIRCUITS AT THE UNIVERSITY OF MINNESOTAIntroductionThermal Analysis of 3D DesignsThermally-Driven Placement and Routing of 3D DesignsPower Grid Design in 3DConclusionELECTRICAL PERFORMANCE OF 3D CIRCUITSIntroduction3D Chip Stack TechnologyElectrical Performance of 3D ContactsSummary and ConclusionTESTING OF 3D CIRCUITSIntroductionYield and 3D IntegrationKnown Good Die (KGD)Wafer Stacking Versus Die StackingDefect Tolerant and Fault Tolerant 3D StacksTHERMAL MANAGEMENT OF VERTICALLY INTEGRATED PACKAGESIntroductionFundamentals of Heat TransferThermal-Packaging ModelingMetrology in Thermal PackagingThermal Packaging ComponentsHeat Removal in Vertically-Integrated PackagesPART V: Applications3D AND MICROPROCESSORSIntroductionDesign of 3D Microprocessor SystemsFabrication of 3D Microprocessor SystemsConclusions3D MEMORIESIntroductionApplicationsRedistribution LayerThrough Wafer InterconnectStackingAdditional IssuesFuture of 3D Memories3D READ-OUT INTEGRATED CIRCUITS FOR ADVANCED SENSOR ARRAYSIntroductionCurrent Activity in 3D ROICsConclusionsPOWER DEVICESIntroductionWafer Level Packaging for Discrete Semiconductor DevicesPackaging for PowerMOSFET DevicesChip Size Packaging of Vertical MOSFETsMetal TWI Process for Vertical MOSFETsFurther Evaluation of the TWI MOSFET CSPsOutlookWIRELESS SENSOR SYSTEMS - THE E-CUBES PROJECTIntroductione-CUBES ConceptEnabling 3D Integration Technologiese-CUBES GHz Radiose-CUBES Applications and RoadmapConclusions
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Autoren-Porträt
Dr. Philip Garrou, from Microelectronic Consultants of North Carolina, specializes in thin film microelectronic materials and applications, prior to which he was Director of Technology and New Business Development for Dow Chemicals - Advanced Electronic Materials business. Heis a fellow of IEEE and IMAPS, has served as Associate Editor of the IEEE Transactions on Advanced Packaging, has authored two microelectronics texts and is co-author of over 75 peer reviewed publications and book chapters.Dr. Christopher Bower is currently a Technical Manager at Semprius Inc., Durham, NC, where he leads a group working on the assembly and wafer-level packaging of advanced multi-junction solar cells for concentrator photovoltaics (CPV). Previously he was a senior scientist at RTI International where he worked on multiple DARPA-funded 3D integration programs. Dr. Bower has authored or co-authored over fifty papers and holds four patents.Dr. Peter Ramm is head of the department Device and 3D Integration of Fraunhofer EMFT in Munich, Germany, where he is responsible for process integration of innovative devices and heterogeneous systems with a specific focus on 3D integration technologies. Dr. Ramm received the physics and Dr. rer. nat. degrees from the University of Regensburg and subsequently worked for Siemens in the DRAM facility where he was responsible for the process integration. In 1988 he joined Fraunhofer IFT in Munich, focusing for over two decades on 3D integration technologies. Peter Ramm is author or co-author of over 100 publications and 24 patents. He receivedthe 'Ashman Award 2009' from the International Electronics Packaging Society (IMAPS) 'For Pioneering Work on 3D IC Stacking and Integration, and leading-edge work on SiGe and Si technologies'. Peter Ramm is Fellow and Life Member of IMAPS, organizing committeeand founding member of IEEE 3DIC conference and co-editor of Wiley´s 'Handbook of Wafer Bonding'.
Bibliographische Angaben
- 2012, XXVI, 773 Seiten, Maße: 17,4 x 25 cm, Kartoniert (TB), Englisch
- Herausgegeben: Philip Garrou, Christopher Bower, Peter Ramm
- Verlag: Wiley-VCH
- ISBN-10: 3527332650
- ISBN-13: 9783527332656
- Erscheinungsdatum: 25.09.2012
Sprache:
Englisch
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