Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors
(Sprache: Englisch)
This book describes fault tolerance techniques based on software and hardware to create hybrid techniques. They are able to reduce overall performance degradation and increase error detection when associated with applications implemented in embedded...
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This book describes fault tolerance techniques based on software and hardware to create hybrid techniques. They are able to reduce overall performance degradation and increase error detection when associated with applications implemented in embedded processors. Coverage begins with an extensive discussion of the current state-of-the-art in fault tolerance techniques. The authors then discuss the best trade-off between software-based and hardware-based techniques and introduce novel hybrid techniques. Proposed techniques increase existing fault detection rates up to 100%, while maintaining low performance overheads in area and application execution time.
Inhaltsverzeichnis zu „Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors “
Introduction.- Background.- Fault Tolerance Techniques for Processors.- Proposed Techniques to Detect Transient Faults in Processors.- Simulation Fault Injection Experimental Results.- Configuration Bitstream Fault Injection Experimental Results.- Radiation Experimental Results.- Conclusions and Future Work.
Bibliographische Angaben
- Autoren: José Rodrigo Azambuja , Fernanda Kastensmidt , Jürgen Becker
- 2016, Softcover reprint of the original 1st ed. 2014, XVIII, 94 Seiten, 11 farbige Abbildungen, Maße: 15,6 x 23,8 cm, Kartoniert (TB), Englisch
- Verlag: Springer, Berlin
- ISBN-10: 3319359975
- ISBN-13: 9783319359977
Sprache:
Englisch
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