Introductory Semiconductor Device Physics for Chip Design and Manufacturing
(Sprache: Englisch)
This text is written within the context of the increasingly interdisciplinary scientific and technical physics/EE environment that challenges today's graduate and advanced senior students. The book thoroughly discusses fundamental semiconductor physics of...
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Produktinformationen zu „Introductory Semiconductor Device Physics for Chip Design and Manufacturing “
This text is written within the context of the increasingly interdisciplinary scientific and technical physics/EE environment that challenges today's graduate and advanced senior students. The book thoroughly discusses fundamental semiconductor physics of devices and wires for physicists, linking these concepts to engineering applications and case studies of actual computer chips. As an added bonus, the book provides a novel textbook treatment of Rent's Rule, which can be used to estimate power dissipation in interconnects. The final chapter discusses nanotechnology, novel materials and nanodevices, and it also offers a comparison of traditional and non-traditional concepts of devices and architectures.
Klappentext zu „Introductory Semiconductor Device Physics for Chip Design and Manufacturing “
An introduction to the fundamentals of semiconductor physics and engineeringThis book discusses fundamental semiconductor physics of devices and on-chip interconnections for physicists and links these concepts to engineering applications and case studies of computer chips. The book is organized in three parts. The first part deals with the representation of information and computation. The second part covers semiconductor device physics within the context of computation. The third part reviews chip design and semiconductor fabrication. The book includes relevant equations, with the aim of closing the gap in the existing literature with actual case studies and engineering applications. Examples are provided in each chapter to illustrate physical and electrical concepts through the use of high-performance silicon technologies.
Introductory Semiconductor Device Physics for Chip Design and Manufacturing:
Provides physical descriptions and illustrations with data visualizations to facilitate intuitive understanding of semiconductor physics, devices and on-chip interconnections
Blends theoretical physics treatment with engineering applications and real case studies for manufactured chips
Presents complementary-metal-oxide-semiconductor (CMOS) transistors in high-performance server microprocessors with static CMOS combinational digital circuit design examples
Offers a rich array of student problem sets, mid-term exams, and final exams with a glossary at the end of the book
M. Y. Lanzerotti, PhD, has over 15 years of engineering experience in designing integrated circuits for high-performance server chips and aerospace applications. Dr. Lanzerotti is Assistant Professor of Physics at Augsburg College and previously held positions as Associate Professor of Computer Engineering at Air Force Institute of Technology, Instructor at Harvard Summer School, Visiting Faculty Fellow at Pacific Lutheran University, Visiting Faculty Fellow at Sapienza University of Rome, and
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Research Staff Member at IBM Thomas J. Watson Research Center. This book is inspired from Dr. Lanzerotti's course, "Introductory Semiconductor Device Physics for Chip Design and Manufacturing," at Harvard Summer School. Dr. Lanzerotti holds physics degrees from Harvard College, the University of Cambridge, and Cornell University. Dr. Lanzerotti holds four U.S. patents, was awarded an IEEE Technical Innovation Award in 2007 and an IBM Outstanding Research Contribution Award in 1998, and was Editor-in-Chief of the IEEE Solid-State Circuits Society Magazine.
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Inhaltsverzeichnis zu „Introductory Semiconductor Device Physics for Chip Design and Manufacturing “
List of Figures xxiList of Tables lixForeword lxxvPreface lxxviiAcknowledgments lxxixAcronyms lxxxiiiIntroduction lxxxviiI.1 J. J. Thomson and the Discovery of the Electron lxxxviiiI.2 Notation xciiI.3 Mathematics xciiI.4 Electricity xcivI.5 The Delay in a Wire is Nonzero xcivI.6 The Delay in a Device is Nonzero xcviI.7 High Performance Silicon Technology xcviiI.8 High Performance Computing (HPC) xcviiiI.9 Organization of this Book xcixPART I REPRESENTATION OF INFORMATION AND COMPUTATION1 Representation of Information and Computation 31.1 Information 41.2 Alan Turing, John von Neumann, and Claude Shannon 241.3 High Performance Silicon Technology 281.4 Catalog of Computation Hardware 582 Computation and Basic Logic Functions 812.1 Rules of Switching Algebra 822.2 Truth Tables and Basic Logic Gates 852.3 Combinational Gates 902.4 Binary Addition 1032.5 Binary Addition with a Full Adder Cell 1042.6 Time-Dependent Properties of Propagating Signals 1072.7 Binary Addition with a Two-bit Adder 1142.8 Binary Addition with a Four-bit Adder 1172.9 Binary Addition with an N-bit Adder 1222.10 Switching Function for the Sum S = S(A;B;C) in a One-bit Full Adder Cell 1222.11 Switching Function for the Output Carry Bit C0 = C0 (A;B;C) in a Full Adder Cell 1242.12 Switching Function for the Sum S = S(A;B;C;C0) in a Full Adder Cell 1252.13 Second Example of a One-bit Binary Adder 1352.14 Catalog of Signal Propagation 1413 Identification of Logic Functions through the Truth Table 1493.1 Switch Model of the Inverter 1503.2 Switch Model of the Buffer 1663.3 Switch Model of the NAND2 Gate 1663.4 Switch Model of the NOR2 Gate 1713.5 Transistor Diagram of Full Adder 1743.6 Dynamic Power Dissipation in an Inverter 1763.7 Dynamic Power Dissipation in an Inverter Chain 1843.8 Catalog of Switching Probabilities 186PART II SEMICONDUCTORS AND SEMICONDUCTOR DEVICES4 Metal-Oxide-Semiconductor (MOS) Capacitor 2474.1 Parallel-Plate Capacitor 2484.2 Metal 2564.3 Semiconductor 2654.4 Insulator 2784.5
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Semiconductor-Insulator Interface (Si - SiO2) 2874.6 The p-n Junction, n-p Junction, and Side View of MOS Physical Structure 2884.7 Visualization of Transistor Behavior 2934.8 Energy Band Diagram for a Metal-Oxide-Semiconductor (MOS) Structure with Vg = 0 V 2944.9 Energy Band Diagram for a Metal-Oxide-Semiconductor (MOS) Structure with Vg > Vt 3034.10 Catalog of Energy Band Diagram Terms and Concepts 3074.11 Catalog of Electrical Components 3135 Three Terminal Devices 3255.1 Complementary Metal Oxide Semiconductor Devices (CMOS) 3255.2 n-type Field-Effect Transistor (nFET) 3315.3 p-type Field-Effect Transistor (pFET) 3415.4 Dependence of Inverter Delay on Metal-Oxide-Semiconductor (MOS) Structure, Electron Mobility, and Hole Mobility 3425.5 Voltage Transfer Curve (VTC) for Input VoltageWaveform and Output Voltage Waveform at an Inverter 3485.6 Dependence of Inverter Rise time and Inverter Fall time on Metal-Oxide-Semiconductor (MOS) Structure, Electron Mobility, and Hole Mobility 3536 Miniaturization of Field-Effect Transistors 3556.1 Gordon Moore's Law 3566.2 Robert Dennard's Scaling Rules 3616.3 Technology Projections of the International Technology Roadmap for Semiconductors (ITRS) 372PART III SEMICONDUCTOR DESIGN AND MANUFACTURING7 On-chip Interconnections 3797.1 Introduction 3807.2 Pi Models for Interconnect 4067.3 Branching: Star Wiring Configuration 4177.4 Effective Materials Properties of Interconnections 4307.5 Back-End-of-Line BEOL Interconnection Architectures 4627.6 Catalog of Hierarchical Back-End-of-Line (BEOL) Interconnection Architectures 4778 Chip Design 4918.1 Introduction 4918.2 Hierarchical Chip Design 5038.3 Application-Specific Integrated Circuit Designs (ASICs), Custom Designs, and Semi-Custom Designs 5128.4 Catalog of Back-End-of-Line (BEOL) Interconnection Implementations 5269 Structures, Yield, and Variation in Semiconductor Manufacturing 5439.1 Introduction 5449.2 Transistor Structures 5469.3 Interconnection Structures 5539.4 Yield 5719.5 Variation in Electrical Properties of Transistors 5909.6 Variation in Electrical Properties of Interconnections 6019.7 Nanotechnology, Nanomanufacturing, and Nanoelectronics 609PART IV PROBLEMS10 Problem Set 1 625Problems 62511 Problem Set 2 633Problems 63312 Mid-Term Exam 645Problems 64513 Mid-Term Exam - II 659Problems 65914 Problem Set 3 669Problems 66915 Final Exam 679Problems 67916 Final Exam - II 691Problems 69117 Appendix: Notation 701Appendix: Notation 70117.1 Notation 70118 Appendix: Additional Examples of Inscriptions 709Appendix: Additional Examples of Inscriptions 70918.1 Colosseo and Pantheon 70918.2 Basilica di S. Agostino 70918.3 St. Peter's Basilica 71318.4 Fontana di Trevi 71418.5 Spanish Steps 71518.6 via Corso and via Mazzarino 716References 719Glossary 775Index 815
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Autoren-Porträt von Robert W. Keyes, Mary Y. Lanzerotti
M. Y. Lanzerotti, PhD, has over 15 years of engineering experience in designing integrated circuits for high-performance server chips and aerospace applications. Dr. Lanzerotti is Assistant Professor of Physics at Augsburg College and previously held positions as Associate Professor of Computer Engineering at Air Force Institute of Technology, Instructor at Harvard Summer School, Visiting Faculty Fellow at Pacific Lutheran University, Visiting Faculty Fellow at Sapienza University of Rome, and Research Staff Member at IBM Thomas J. Watson Research Center. This book is inspired from Dr. Lanzerotti's course, "Introductory Semiconductor Device Physics for Chip Design and Manufacturing," at Harvard Summer School. Dr. Lanzerotti holds physics degrees from Harvard College, the University of Cambridge, and Cornell University. Dr. Lanzerotti holds four U.S. patents, was awarded an IEEE Technical Innovation Award in 2007 and an IBM Outstanding Research Contribution Award in 1998, and was Editor-in-Chief of the IEEE Solid-State Circuits Society Magazine.
Bibliographische Angaben
- Autoren: Robert W. Keyes , Mary Y. Lanzerotti
- 2018, 848 Seiten, mit Abbildungen, Maße: 16,8 x 25 cm, Gebunden, Englisch
- Verlag: Wiley & Sons
- ISBN-10: 047062454X
- ISBN-13: 9780470624548
- Erscheinungsdatum: 14.01.2016
Sprache:
Englisch
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