Low Power and Process Variation Aware SRAM and Cache Design
(Sprache: Englisch)
This volume examines process variability and power management for embedded memories. It provides thorough background on voltage scaling and the reliability effects on memories, while describing memory behavior at different voltages and frequencies.
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This volume examines process variability and power management for embedded memories. It provides thorough background on voltage scaling and the reliability effects on memories, while describing memory behavior at different voltages and frequencies.
Klappentext zu „Low Power and Process Variation Aware SRAM and Cache Design “
This book addresses process variability and power management for embedded memories, which are becoming dominant components in today's Systems on Chip (SoCs). It provides thorough background on voltage scaling and the reliability effects on memories, while describing memory behavior at different voltages and frequencies. The authors describe a cross-layer approach, simultaneously targeting the manufacturing of devices, the inner-design of the memory circuits, as well as the way they are architected into a system. This approach enables the design of reliable, power-efficient systems in which memories are dominating area, power, and performance.
Inhaltsverzeichnis zu „Low Power and Process Variation Aware SRAM and Cache Design “
Introduction.- SCPS Cache.- RDC-Cache.- IDC-Cache.- VTD-Cache.- Conclusions.
Bibliographische Angaben
- Autoren: Sasan Avesta , Fadi Kurdahi , Ahmed Eltawil
- 2016, 1st ed., 200 Seiten, 100 Abbildungen, Maße: 15,5 x 23,5 cm, Gebunden, Englisch
- Verlag: Springer, New York
- ISBN-10: 146142271X
- ISBN-13: 9781461422716
- Erscheinungsdatum: 01.12.2015
Sprache:
Englisch
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