Low Power Wallace Multiplier
A Design Prospective
(Sprache: Englisch)
Multipliers are basic building blocks of many VLSI computational units. The performance of such VLSI circuits depends on the performance of multipliers. A multiplier is also one of the key hardware blocks in most digital signal processing (DSP) systems....
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Multipliers are basic building blocks of many VLSI computational units. The performance of such VLSI circuits depends on the performance of multipliers. A multiplier is also one of the key hardware blocks in most digital signal processing (DSP) systems. Typical in DSP applications, where a multiplier plays an important role include digital filtering, digital communications and spectral analysis. Since multipliers are rather complex circuits and must typically operate at a high system clock rate, reducing the delay of a multiplier is an essential part of satisfying the overall design. So designing a fast multiplier is a challenging task for VLSI designers. There are various types of multipliers are available such as the array multiplier, carry-save multiplier, Wallace-tree multiplier, etc. Among this Wallace-tree multiplier or Wallace multiplier has been a very popular design due to its fast speed and low power. In this book, a design prospective of a low power Wallace Multiplier has been presented.
Autoren-Porträt von Inamul Hussain, Saurabh Choudhury, Manish Kumar
Hussain, InamulInamul Hussain is the youngest son of Siddique Hussain and Rukiya Khanam and pursuing Ph.D. in the Department of EE, NIT Silchar (an institute of national importance), India. His research area includes low power VLSI, CMOS and CNTFET-based circuits and systems design. He has publications in reputed journals and international conferences.
Bibliographische Angaben
- Autoren: Inamul Hussain , Saurabh Choudhury , Manish Kumar
- 2020, 64 Seiten, Maße: 22 cm, Kartoniert (TB), Englisch
- Verlag: LAP Lambert Academic Publishing
- ISBN-10: 6200783411
- ISBN-13: 9786200783417
Sprache:
Englisch
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