Model and Design of Bipolar and MOS Current-Mode Logic
CML, ECL and SCL Digital Circuits
(Sprache: Englisch)
Current-Mode digital circuits have been extensively analyzed and used since the early days of digital ICs. In particular, bipolar Current-Mode digital circuits emerged as an approach to realize digital circuits with the highest speed. Together with its...
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Klappentext zu „Model and Design of Bipolar and MOS Current-Mode Logic “
Current-Mode digital circuits have been extensively analyzed and used since the early days of digital ICs. In particular, bipolar Current-Mode digital circuits emerged as an approach to realize digital circuits with the highest speed. Together with its speed performance, CMOS Current-Mode logic has been rediscovered to allow logic gates implementations which, in contrast to classical VLSI CMOS digital circuits, have the feature of low noise level generation. Thus, CMOS Current-Mode gates can be efficiently used inside analog and mixed-signal ICs, which require a low noise silicon environment. For these reasons, until today, many works and results have been published which reinforce the importance of Current-Mode digital circuits. In the topic of Current-Mode digital circuits, the authors spent a lot of effort in the last six years, and their original results highly enhanced both the modeling and the related design methodologies. Since the fundamental Current-Mode logic building block is the classical differential amplifier, the winning idea, that represents the starting point of the authors' research, was to change the classical point of view typically followed in the investigation and design of Current-Mode digital circuits. In particular, they properly exploited classical paradigms developed and used in the analog circuit domain (a topic in which one of the authors maturated a great experience).
Inhaltsverzeichnis zu „Model and Design of Bipolar and MOS Current-Mode Logic “
Acknowledgment. Preface.1. Devices Modeling for Digital Circuits.
1.1. PN JUNCTION.
1.1.1. Reverse Bias Condition.
1.1.2. Foward Bias Condition.
1.2. BIPOLAR-JUNCTION TRANSISTORS.
1.2.1 Basic Operation.
1.2.2. Early Effect or Base Width Modulation.
1.2.3. Charge Effects in the Bipolar Transistor.
1.2.4. Small Signal Model.
1.3. MOS TRANSISTORS.
1.3.1. Basic Operation.
1.3.2. Triode or Linear Region.
1.3.3. Saturation or Active Region.
1.3.4. Body Effect.
1.3.5. p-channel Transistors.
1.3.6. Charge Effects in Saturation Region.
1.3.7 Charge Effects in Triode Region.
1.3.8. Charge Effects in Cutoff Region.
1.3.9. Small Signal Model.
1.3.10. Second Order Effects in MOSFET Modeling.
2. Current-Mode Digital Circuits.
2.1. The bipolar Current-mode inverter: basic principles.
2.2. The bipolar Current-mode inverter: Input-Output CharacteristicS and noise margin.
2.2.1. Differential input/output.
2.2.2. Single-ended input/output..
2.2.3. Considerations on the non zero input current.
2.2.4. Remarks and comparison of differential/single-ended gates.
2.3. The buffered bipolar Current-mode (ECL) inverter.
2.4. The MOS Current-mode inverter.
2.4.1. Static modeling of the PMOS active load.
2.4.2. Input-output characteristics.
2.4.3. Evaluation of the noise margin.
2.4.4. Validation of the static model. .
2.4.5. The buffered MOS Current-Mode inverter and remarks.
2.5. Fundamental Current-mode logic gates.
2.5.1 Principle of operation of Current-Mode gates: the series gating concept.
2.5.2. Some examples of Current-Mode series gates.
2.5.3. Supply voltage limitations in bipolar Current-Mode gates.
2.5.4. MOS Current-Mode series gates and supply voltage limitations.
2.6. Typical applications of Current-mode circuits.
2.6.1. Radio Frequency applications.
2.6.2. Optic-fiber communications.
2.6.3. High-resolution mixed-signal ICs.
3. Methodologies for complex Current-mode logic gates.
3.1. BASIC CONCEPTS ON THE DESIGN OF A SERIES
... mehr
GATE.
3.1.1. Evaluation of function F(X1...Xn) implemented by a given topology.
3.1.2. Series-gate implementation of an assigned function F(X1...Xn).
3.1.3. Limitations of the general series-gate design approach.
3.2. A GRAPHICAL REDUCTION METHOD.
3.2.1. Basic concepts on the graphical approach in [CJ89].
3.2.2. A design example.
3.3. an analytical formulation of the design strategy IN [CJ89].
3.3.1. Analytical interpretation of CPE/NPE.
3.3.2. Analytical simplification through CPE/NPE: an example.
3.3.3. Circuit implementation of the simplified function after CPE-NPE.
3.4. A VEM-BASED REDUCTION METHOD.
3.5. INPUT ORDERING VERSUS DESIGN GOAL.
4. Modeling of Bipolar Current-mode gates.
4.1. Introduction to Modeling methodologies.
4.2. AN EFFICIENT APPROACH FOR CML GATES.
4.3. Simple modeling of THE CML inverter.
4.3.1. Accuracy of the CML simple model.
4.4. Accurate modeling of THE CML inverter.
4.4.1. Accuracy of the CML accurate model.
4.5. Simple AND ACCURATE modeling of THE ECL inverter.
4.5.1. Validation and improvement of the ECL model.
4.6. SIMPLE modeling of bipolar CML MUX/XOR gates.
4.6.1. Validation of the MUX/XOR model.
4.6.2.Extension to the MUX/XOR when upper transistors switch.
4.7. ACCURATE modeling of bipolar CML MUX/XOR gates AND EXTENSION TO ECL GATES.
4.8. EVALUATION OF CML/ecl GATES INPUT CAPACITANCE.
4.9. bipolar Current-mode D Latch.
5. Optimized Design of Bipolar Current-mode gates.
5.1. Introduction to optimized methodology in cml gates.
5.2. OPTIMIZED DESIGN OF THE CML INVERTER.
5.2.1. Design with minimum transistor area.
5.2.2. Design with non-minimum transistor area.
5.2.3. Design examples.
5.3. OPTIMIZED DESIGN OF THE ECL INVERTER.
5.4. COMPARISON BETWEEN THE CML AND THE ECL INVERTER.
5.5. OPTIMIZED DESIGN OF BIPOLAR CURRENT-MODE MUX/XOR AND D LATCH.
5.5.1. Design of MUX/XOR CML gates with minimum transistor area.
5.5.2. Design of MUX/XOR CML gates with non-minimum transistor area and examples.
5.5.3. Design of the CML D latch.
5.5.4. Design examples.
5.6. SUMMARY AND REMARKS.
6. Modeling of MOS current-mode gates.
6.1. INTRODUCTION TO THE DELAY MODELING OF MOS CURRENT-MODE GATES.
6.2. MODELING OF THE SOURCE-COUPLED INVERTER.
6.2.1. Circuit model of the PMOS active load.
6.2.2. Delay model of the SCL inverter for a step inpu.
6.2.3. Extension of the delay model to arbitrary input waveforms.
6.3. MODELING OF THE SOURCE-COUPLED INVERTER WITH OUTPUT BUFFERS.
6.4. MODELING OF THE SOURCE-COUPLED MUX/XOR GATE.
6.4.1. Delay model of the MUX/XOR gate without output buffer.
6.4.2. Validation of the model of MUX/XOR gate without output buffer.
6.4.3. MUX/XOR with the upper transistor switching.
6.4.4. Delay model of the MUX/XOR gate with output buffers.
6.5. EVALUATION OF SCL GATES INPUT CAPACITANCE AND EXTENSION TO THE D Latch.
7. Optimized Design of MOS Current-mode gates.
7.1. Introduction to optimized DESIGN OF scl gates.
7.2. optimized design methodology in scl gates without output buffers.
7.2.1. Power-efficient design.
7.2.2. High-speed design.
7.2.3. Low-power design.
7.2.4. Remarks on the delay dependence on bias current and logic swing.
7.3. TRANSISTOR SIZING TO MEET NOISE MARGIN SPECIFICATION.
7.3.1. Design criteria for VSWING and AV to meet a noise margin specification.
7.3.2. Transistor sizing versus ISS.
7.3.3. Summary and remarks on the transistor sizing versus ISS.
7.4. OPTIMIZED DESIGN OF THE SOURCE-COUPLED INVERTER.
7.4.1. Delay expression versus bias current and logic swing in region M.
7.4.2. Delay expression versus bias current and logic swing in region L and H.
7.4.3. Extension of the delay model in the region M to region L and H: a unified expression of delay and remarks.
7.4.4. Design criteria and examples.
7.4.5. Intuitive understanding of the delay dependence on logic swing and voltage gain in practical design cases.
7.5. OPTIMIZED DESIGN OF THE SOURCE-COUPLED INVERTER WITH OUTPUT BUFFERS.
7.5.1. Buffer used as a level shifter.
7.5.2. Buffer used to improve speed.
7.6. OPTIMIZED DESIGN OF THE SOURCE-COUPLED MUX/XOR and d latch.
7.6.1. MUX/XOR delay expression versus bias current and logic swing with the lower transistors switching.
7.6.2. MUX/XOR delay expression versus bias current and logic swing for input applied to upper transistors.
7.6.3. Delay dependence on logic swing.
7.6.4. Extension to D latch.
7.7. OPTIMIZED DESIGN OF THE SOURCE-COUPLED MUX/XOR and d latch WITH OUTPUT BUFFERS.
7.8. COMPARISON OF GATES ANALYZED AND EXTENSION TO ARBITRARY SCL LOGIC GATES.
8. applications and remarks on current-mode digital circuits.
8.1. Ring Oscillators.
8.1.1. Bipolar CML ring oscillators.
8.1.2. Validation of the oscillation frequency in a CML ring oscillator.
8.1.3. Remarks on the oscillation amplitude in a CML ring oscillator.
8.1.4. CMOS SCL ring oscillators.
8.2. Frequency dividers.
8.2.1. Design of the first stage.
8.2.2. Design of successive stages.
8.2.3. Design considerations and examples.
8.3. Low-voltage bipolar Current-mode topologies.
8.3.1. Low-voltage CML by means of the triple-tail cell.
8.3.2. Analysis of the low-voltage CML D latch static operation.
8.3.3. Delay of the low-voltage CML D latch.
8.3.4. Comparison of the low-voltage and traditional CML D latch designed for high speed.
8.3.5. Comparison of the low-voltage and traditional CML D latch designed for a low power consumption.
8.3.6. Summary of results and remarks.
8.4. Optimized design strategies for CASCADED BIPOLAR CURRENT-MODE GATES.
8.4.1. Design of CML non-critical paths with a constraint on the overall bias current.
8.4.2. Design of CML critical paths with a constraint on the overall bias current.
8.4.3. Design of CML critical paths with a constraint on the overall bias current and equal transistors' emitter area.
REFERENCES. ABOUT THE AUTHORS.
3.1.1. Evaluation of function F(X1...Xn) implemented by a given topology.
3.1.2. Series-gate implementation of an assigned function F(X1...Xn).
3.1.3. Limitations of the general series-gate design approach.
3.2. A GRAPHICAL REDUCTION METHOD.
3.2.1. Basic concepts on the graphical approach in [CJ89].
3.2.2. A design example.
3.3. an analytical formulation of the design strategy IN [CJ89].
3.3.1. Analytical interpretation of CPE/NPE.
3.3.2. Analytical simplification through CPE/NPE: an example.
3.3.3. Circuit implementation of the simplified function after CPE-NPE.
3.4. A VEM-BASED REDUCTION METHOD.
3.5. INPUT ORDERING VERSUS DESIGN GOAL.
4. Modeling of Bipolar Current-mode gates.
4.1. Introduction to Modeling methodologies.
4.2. AN EFFICIENT APPROACH FOR CML GATES.
4.3. Simple modeling of THE CML inverter.
4.3.1. Accuracy of the CML simple model.
4.4. Accurate modeling of THE CML inverter.
4.4.1. Accuracy of the CML accurate model.
4.5. Simple AND ACCURATE modeling of THE ECL inverter.
4.5.1. Validation and improvement of the ECL model.
4.6. SIMPLE modeling of bipolar CML MUX/XOR gates.
4.6.1. Validation of the MUX/XOR model.
4.6.2.Extension to the MUX/XOR when upper transistors switch.
4.7. ACCURATE modeling of bipolar CML MUX/XOR gates AND EXTENSION TO ECL GATES.
4.8. EVALUATION OF CML/ecl GATES INPUT CAPACITANCE.
4.9. bipolar Current-mode D Latch.
5. Optimized Design of Bipolar Current-mode gates.
5.1. Introduction to optimized methodology in cml gates.
5.2. OPTIMIZED DESIGN OF THE CML INVERTER.
5.2.1. Design with minimum transistor area.
5.2.2. Design with non-minimum transistor area.
5.2.3. Design examples.
5.3. OPTIMIZED DESIGN OF THE ECL INVERTER.
5.4. COMPARISON BETWEEN THE CML AND THE ECL INVERTER.
5.5. OPTIMIZED DESIGN OF BIPOLAR CURRENT-MODE MUX/XOR AND D LATCH.
5.5.1. Design of MUX/XOR CML gates with minimum transistor area.
5.5.2. Design of MUX/XOR CML gates with non-minimum transistor area and examples.
5.5.3. Design of the CML D latch.
5.5.4. Design examples.
5.6. SUMMARY AND REMARKS.
6. Modeling of MOS current-mode gates.
6.1. INTRODUCTION TO THE DELAY MODELING OF MOS CURRENT-MODE GATES.
6.2. MODELING OF THE SOURCE-COUPLED INVERTER.
6.2.1. Circuit model of the PMOS active load.
6.2.2. Delay model of the SCL inverter for a step inpu.
6.2.3. Extension of the delay model to arbitrary input waveforms.
6.3. MODELING OF THE SOURCE-COUPLED INVERTER WITH OUTPUT BUFFERS.
6.4. MODELING OF THE SOURCE-COUPLED MUX/XOR GATE.
6.4.1. Delay model of the MUX/XOR gate without output buffer.
6.4.2. Validation of the model of MUX/XOR gate without output buffer.
6.4.3. MUX/XOR with the upper transistor switching.
6.4.4. Delay model of the MUX/XOR gate with output buffers.
6.5. EVALUATION OF SCL GATES INPUT CAPACITANCE AND EXTENSION TO THE D Latch.
7. Optimized Design of MOS Current-mode gates.
7.1. Introduction to optimized DESIGN OF scl gates.
7.2. optimized design methodology in scl gates without output buffers.
7.2.1. Power-efficient design.
7.2.2. High-speed design.
7.2.3. Low-power design.
7.2.4. Remarks on the delay dependence on bias current and logic swing.
7.3. TRANSISTOR SIZING TO MEET NOISE MARGIN SPECIFICATION.
7.3.1. Design criteria for VSWING and AV to meet a noise margin specification.
7.3.2. Transistor sizing versus ISS.
7.3.3. Summary and remarks on the transistor sizing versus ISS.
7.4. OPTIMIZED DESIGN OF THE SOURCE-COUPLED INVERTER.
7.4.1. Delay expression versus bias current and logic swing in region M.
7.4.2. Delay expression versus bias current and logic swing in region L and H.
7.4.3. Extension of the delay model in the region M to region L and H: a unified expression of delay and remarks.
7.4.4. Design criteria and examples.
7.4.5. Intuitive understanding of the delay dependence on logic swing and voltage gain in practical design cases.
7.5. OPTIMIZED DESIGN OF THE SOURCE-COUPLED INVERTER WITH OUTPUT BUFFERS.
7.5.1. Buffer used as a level shifter.
7.5.2. Buffer used to improve speed.
7.6. OPTIMIZED DESIGN OF THE SOURCE-COUPLED MUX/XOR and d latch.
7.6.1. MUX/XOR delay expression versus bias current and logic swing with the lower transistors switching.
7.6.2. MUX/XOR delay expression versus bias current and logic swing for input applied to upper transistors.
7.6.3. Delay dependence on logic swing.
7.6.4. Extension to D latch.
7.7. OPTIMIZED DESIGN OF THE SOURCE-COUPLED MUX/XOR and d latch WITH OUTPUT BUFFERS.
7.8. COMPARISON OF GATES ANALYZED AND EXTENSION TO ARBITRARY SCL LOGIC GATES.
8. applications and remarks on current-mode digital circuits.
8.1. Ring Oscillators.
8.1.1. Bipolar CML ring oscillators.
8.1.2. Validation of the oscillation frequency in a CML ring oscillator.
8.1.3. Remarks on the oscillation amplitude in a CML ring oscillator.
8.1.4. CMOS SCL ring oscillators.
8.2. Frequency dividers.
8.2.1. Design of the first stage.
8.2.2. Design of successive stages.
8.2.3. Design considerations and examples.
8.3. Low-voltage bipolar Current-mode topologies.
8.3.1. Low-voltage CML by means of the triple-tail cell.
8.3.2. Analysis of the low-voltage CML D latch static operation.
8.3.3. Delay of the low-voltage CML D latch.
8.3.4. Comparison of the low-voltage and traditional CML D latch designed for high speed.
8.3.5. Comparison of the low-voltage and traditional CML D latch designed for a low power consumption.
8.3.6. Summary of results and remarks.
8.4. Optimized design strategies for CASCADED BIPOLAR CURRENT-MODE GATES.
8.4.1. Design of CML non-critical paths with a constraint on the overall bias current.
8.4.2. Design of CML critical paths with a constraint on the overall bias current.
8.4.3. Design of CML critical paths with a constraint on the overall bias current and equal transistors' emitter area.
REFERENCES. ABOUT THE AUTHORS.
... weniger
Bibliographische Angaben
- Autoren: Massimo Alioto , Gaetano Palumbo
- 2010, XV, 318 Seiten, Maße: 16,4 x 23,9 cm, Kartoniert (TB), Englisch
- Verlag: Springer, Berlin
- ISBN-10: 1441952586
- ISBN-13: 9781441952585
Sprache:
Englisch
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