MODELLING AND DESIGN OF MODIFIED SDM BASED NETWORK ON CHIP
(Sprache: Englisch)
Moore's law has driven the scaling of digital electronic devicesdimensions and performances over the last 50 years. As a result, logic components in a System-On-Chip (SoC) have shown dramatic performance improvement. On the other hand, an on-chip...
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Moore's law has driven the scaling of digital electronic devicesdimensions and performances over the last 50 years. As a result, logic components in a System-On-Chip (SoC) have shown dramatic performance improvement. On the other hand, an on-chip interconnects which was considered only as a parasitic load before 1990s became the real performance bottleneck due to its extremely reduced cross section dimension. The ever decreasing interconnects cross section dimensions give rise to increase in resistance. Putting all these together, degradation of the RC time constant of on-chip metal wires becomes more serious. As a result, the continuous performance degradation of on-chip Cu/low k interconnects is one of the greatest challenges to keep Moore's law alive while the scaling of transistors dimension has provided relentless delay improvement.
Autoren-Porträt von Amar Babu, John Bedford Solomon, G. M. V. Prasad
Babu, AmarDr. Y. Amar Babu received the B.Tech., degree in Electronics and Communication Engineering in the year 1999 from Velagapudi Ramakrishna Siddhartha Engineering College, Acharya Nagarjuna University, Guntur, Andhra Pradesh, India. He obtained M.E., degree in VLSI Design in the year 2002 from PSG College of Technology, Bharathiar University.
Bibliographische Angaben
- Autoren: Amar Babu , John Bedford Solomon , G. M. V. Prasad
- 2021, 168 Seiten, Maße: 22 cm, Kartoniert (TB), Englisch
- Verlag: LAP Lambert Academic Publishing
- ISBN-10: 6203471038
- ISBN-13: 9786203471038
Sprache:
Englisch
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