Open Source TCAD/EDA for Compact Modeling

Preface.

Introduction: Wladek Grabinski, GMC Suisse, Daniel Tomaszewski, ITE Warsaw

Chapter 1: Numerical Cogenda TCAD MOSFET Device Simulations.
Tutorial to Genius Device Simulator. Physics of Device Simulation. Numerical Method in Device Simulation. Device simulation: A MOS example.

Chapter 2: Semiconductor Device Simulation Using DEVSIM; Juan E. Sanchez.
Introduction. BJT Physics. BJT Simulation. Conclusion and Future Work.

Chapter 3: Device Level Parameter Extraction; Daniel Tomaszewski, Wladek Grabinski.
Introduction. Parameter extractors overview. General optimization algorithms. Profile1d: open source extractor. Examples: Diode, MOSCAP, BJT, MOSFET, IC Subcircuit. Summary. Appendix: List Profile1d  commands.

Chapter 4: Schematic entry and circuit simulation with Qucs; Mike Brinson.
Introduction. The Qucs graphical user interface. Basic principles of circuit schematic capture. Qucs parameter sweep techniques. Qucs small signal AC circuit and noise simulation. Qucs transient simulation. Qucs subcircuits. Including SPICE netlists in Qucs schematic diagrams. Qucs post-simulation data processing. Summary.

Chapter 5: Qucs modeling and simulation of analog/RF devices and circuits; Mike Brinson.
Introduction. Circuit and system modeling using macromodels. Qucs equation-defined device models. Qucs and QucsStudio compact model development with the ADMS Verilog-A model synthesizer/compiler. QucsStudio implementation. More RF examples. From Qucs to QucsStudio: future directions in analog simulation and device modeling. Summary

Chapter 6: Simulations of Digital IC Blocks; Zia Abbas, Antonio Mastrandrea, Francesco Menichelli and Mauro Olivieri.
Basics on Nano-scale Digital CMOS Analysis: Propagation Delay and Static Power. Basic Ngspice Delay and Leakage Current Analysis. Automated Delay Characterization of CMOS Standard Cells. Automated Leakage Current Characterization In CMOS Standard Cells.

Wladek Grabinski received the Ph.D. degree from the Institute of Electron Technology, Warsaw, Poland, in 1991. From 1991 to 1998 he was a Research Assistant at the Integrated Systems Lab, ETH Zürich, Switzerland, supporting the CMOS and BiCMOS technology developments by electrical characterization of the processes and devices. From 1999 to 2000, he was with LEG, EPF Lausanne, and was engaged in the compact MOSFET model developments supporting numerical device simulation and parameter extraction. Later, he was a technical staff engineer at Motorola, and subsequently at Freescale Semiconductor, Geneva Modeling Center, Switzerland. He is now an consultant responsible for modeling, characterization and parameter extraction of MOS transistors for the design of RF CMOS circuits. He is currently consulting on the development of next-generation compact models for the 65¿32-nm-technology very large scale integration (VLSI) circuit simulation. His current research interests are in high-frequency characterization, compact modeling and its Verilog-A standardization as well as device numerical simulations of MOSFETs for analog/RF low power applications. He is an editor of the reference modeling book Transistor Level Modeling for Analog/RF IC Design and also authored or coauthored more than 50 papers. Wladek has served as a member in IEEE EDS Compact Modeling Committee, organization committee of ESSDERC/ESSDERC, TPC of SBMicro, SISPAD, MIXDES Conferences. He also serves as European representative for the ITRS Modeling and Simulation working group. Wladek is involved in activities of the MOS-AK/GSA compact modeling group and serves as a coordinating manager since 1999.