Self timed Null Convention Logic Approaches
(Sprache: Englisch)
Nowadays, the design of low power compact designs grabs higher attention. Hence, Low power gadgets finds more demand. Clock is the main source for power consumption. Lot of research is going on in the design of clock less architectures. Self timed...
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Nowadays, the design of low power compact designs grabs higher attention. Hence, Low power gadgets finds more demand. Clock is the main source for power consumption. Lot of research is going on in the design of clock less architectures. Self timed approaches are the best choice in this aspect. Glitches will contribute significantly for the total power consumption. With the aid of self timed Delay Insensitive approaches, differential path delays can be eliminated and hence glitch power can be nullified.
Autoren-Porträt von Sudhakar Jyothula, Mallikarjuna Prasad Avala, Ajit Kumar Panda
Jyothula, SudhakarSudhakar Jyothula was born in Andhra Pradesh, India in 1981 and received Ph.D in Low Power VLSI area from the department of Electronics & Communication Engineering, JNTU Kakinada in 2016. Dr. Sudhakar is a life member in Institution of Electronics and Telecommunication Engineers (IETE) and Institution of Engineers, India.
Bibliographische Angaben
- Autoren: Sudhakar Jyothula , Mallikarjuna Prasad Avala , Ajit Kumar Panda
- 2018, 156 Seiten, Maße: 22 cm, Kartoniert (TB), Englisch
- Verlag: LAP Lambert Academic Publishing
- ISBN-10: 6139881196
- ISBN-13: 9786139881192
Sprache:
Englisch
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