SystemVerilog for Design and Verification using UVM
From RTL to Synthesis
(Sprache: Englisch)
Here is a complete guide to using SystemVerilog for ASIC design, from conception to RTL coding, to synthesis and verification. It covers the practical essentials needed for design, verification, synthesis and static timing analysis.
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Here is a complete guide to using SystemVerilog for ASIC design, from conception to RTL coding, to synthesis and verification. It covers the practical essentials needed for design, verification, synthesis and static timing analysis.
Klappentext zu „SystemVerilog for Design and Verification using UVM “
This book is an "A-Z" guide to using SystemVerilog for ASIC design, from conception to RTL coding, to synthesis and verification. Readers will benefit from a thorough introduction to the powerful constructs and features of SystemVerilog. In addition, the verification methodology of Universal Verification Methodology (UVM) is used to build test-benches that allow for verification of complicated designs and synthesis basics are discussed, using the Synopsys Design Compiler (DC). To complete this book's package as a practical guide, readers are introduced to the fundamentals of static timing analysis.
Inhaltsverzeichnis zu „SystemVerilog for Design and Verification using UVM “
The SystemVerilog language.- Designing with SystemVerilog.- Verification with SytemVerilog.- Building environment and the DUT.- Synthesis.- Timing analysis.
Autoren-Porträt von Mark A. Azadpour
Mark A. Aazadpour is a senior staff member at Seagate Technology, LLC.
Bibliographische Angaben
- Autor: Mark A. Azadpour
- 2015, 1st ed., 300 Seiten, 100 Schwarz-Weiß-Abbildungen, 100 Abbildungen, Maße: 15,5 x 5 cm, Gebunden, Englisch
- Verlag: Springer
- ISBN-10: 1461417570
- ISBN-13: 9781461417576
- Erscheinungsdatum: 01.12.2015
Sprache:
Englisch
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