Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits
(Sprache: Englisch)
This book provides theoretical and practical background on the implementation of in-situ delay monitors. It details dynamic and adaptive voltage scaling techniques as well as the impact of variations at shrinking technology nodes.
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This book provides theoretical and practical background on the implementation of in-situ delay monitors. It details dynamic and adaptive voltage scaling techniques as well as the impact of variations at shrinking technology nodes.
Klappentext zu „Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits “
Increasing performance demands in integrated circuits, together with limited energy budgets, force IC designers to find new ways of saving power. One innovative way is the presented adaptive voltage scaling scheme, which tunes the supply voltage according to the present process, voltage and temperature variations as well as aging. The voltage is adapted "on the fly" by means of in-situ delay monitors to exploit unused timing margin, produced by state-of-the-art worst-case designs. This book discusses the design of the enhanced in-situ delay monitors and the implementation of the complete control-loop comprising the monitors, a control-logic and an on-chip voltage regulator. An analytical Markov-based model of the control-loop is derived to analyze its robustness and stability. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits provides an in-depth assessment of the proposed voltage scaling scheme when applied to an arithmetic and an image processing circuit. This book is written for engineers interested in adaptive techniques for low-power CMOS circuits.
Inhaltsverzeichnis zu „Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits “
1 Introduction.
2 Sources of Variation. 2.1 Process Variations. 2.2 Voltage Variations. 2.3 Temperature Variations. 2.4 Aging. 2.5 Summary.
3 Related Work. 3.1 Dynamic Voltage Scaling. 3.2 Adaptive Voltage Scaling.
4 Adaptive Voltage Scaling by In-situ Delay Monitoring. 4.1 Principle of Operation. 4.2 Overall AVS Control Loop.
5 Design of In-situ Delay Monitors. 5.1 Delay-element based Pre-Error Flip-Flop. 5.2 Duty-Cycle based Pre-Error Flip-Flops. 5.3 Comparison of In-situ Delay Monitors.
6 Modeling the AVS Control Loop. 6.1 Simulation Methodology. 6.2 Markov Model of the Pre-Error AVS System. 6.3 Stability of the Control Loop.
7 Evaluation of the Pre-Error AVS Approach. 7.1 Power Saving Potential and Reliability. 7.2 Application of Pre-Error AVS for an Image Processing Circuit.
8 Conclusion.
A Appendix. A.1 Mathematical Derivation: Path Delay under Local Variations. A.2 2-D DCT Transform.
References.
Autoren-Porträt von Martin Wirnshofer
Martin Wirnshofer received the Dipl.-Ing. degree in Electrical Engineering in 2007 from the Technische Universität München (TUM), Germany. His research on voltage reference circuits earned him the Outstanding Thesis Award by the German Association of Electrical Engineers (VDE). From 2007 to 2008 he was an analog designer with the Embedded Flash Memory Group at Infineon Technologies AG, Munich. Since 2008 he is a doctoral researcher at the Institute for Technical Electronics at TUM and has recently finished his Ph.D. project. He received the Excellence in Teaching Award by the Faculty of Electrical Engineering in 2010 and has authored and co-authored numerous international conference and journal publications. His research interests include low-power and low-voltage circuit design, adaptive circuit techniques and design methodologies for the nanoscale CMOS era. He is a member of the IEEE and the German Association of Electrical Engineers.
Bibliographische Angaben
- Autor: Martin Wirnshofer
- 2015, 2013., 83 Seiten, Maße: 23,5 cm, Kartoniert (TB), Englisch
- Verlag: Springer Netherlands
- ISBN-10: 9401783675
- ISBN-13: 9789401783675
Sprache:
Englisch
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