VLSI Chip Design with the Hardware Description Language VERILOG (PDF)
An Introduction Based on a Large RISC Processor Design
(Sprache: Englisch)
This book introduces to modern design of large chips. A powerful RISC processor in the range of a SPARC is apecified in a hardware description language (HDL), it is developed hierarchically and is finally sent as a gate model to the silicon vendor LSI Logic...
sofort als Download lieferbar
eBook (pdf)
53.49 €
26 DeutschlandCard Punkte
sammeln
- Lastschrift, Kreditkarte, Paypal, Rechnung
- Kostenloser tolino webreader
Produktdetails
Produktinformationen zu „VLSI Chip Design with the Hardware Description Language VERILOG (PDF)“
This book introduces to modern design of large chips. A powerful RISC processor in the range of a SPARC is apecified in a hardware description language (HDL), it is developed hierarchically and is finally sent as a gate model to the silicon vendor LSI Logic for production. The resulting processor on a semi-custom gate-array chip with more than 50.000 used gates and an efficiency of up to 40 MIPS is tested on an automatic test equipment and a testboard. The book also introduces thoroughly to the HDL VERILOG. The included disk contains more than 40 small and medium sized executable VERILOG examples, the large processor models and the VERILOG simulator VeriWell running on PC or SPARC.
Bibliographische Angaben
- Autor: Ulrich Golze
- 2013, 1996, 360 Seiten, Englisch
- Verlag: Springer Berlin Heidelberg
- ISBN-10: 3642610013
- ISBN-13: 9783642610011
- Erscheinungsdatum: 11.11.2013
Abhängig von Bildschirmgröße und eingestellter Schriftgröße kann die Seitenzahl auf Ihrem Lesegerät variieren.
eBook Informationen
- Dateiformat: PDF
- Größe: 27 MB
- Ohne Kopierschutz
- Vorlesefunktion
Sprache:
Englisch
Kommentar zu "VLSI Chip Design with the Hardware Description Language VERILOG"
0 Gebrauchte Artikel zu „VLSI Chip Design with the Hardware Description Language VERILOG“
| Zustand | Preis | Porto | Zahlung | Verkäufer | Rating |
|---|
Schreiben Sie einen Kommentar zu "VLSI Chip Design with the Hardware Description Language VERILOG".
Kommentar verfassen