Architecture of Computing Systems -- ARCS 2016

Configurable and In-Memory Accelerators.- TowardsMulticore Performance with Configurable Computing Units.- Design and Evaluationof a Processing-in-Memory Architecture for the Smart Memory Cube.- Network-on-Chipand Secure Computing Architectures.- CASCADE: Congestion Aware Switchable CycleAdaptive Detection Router.- An Alternating Transmission Scheme for DetectionRouting based Network-on-Chips.- Exzess: Hardware-based RAM Encryption againstPhysical Memory Disclosure.- Hardware-Assisted Context Management forAccelerator Virtualization: A Case Study with RSA.- Cache Architectures andProtocols Adaptive Cache Structures.- Optimization of a Linked Cache CoherenceProtocol for Scalable Manycore Coherence.- Mapping of Applications onHeterogeneous.- Architectures and Real-Time Tasks on Multiprocessors Genericalgorithmic scheme for 2D stencil applications on heterogeneous hybrid machines.-GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive LoadBalancing.- Task Variants with Different Scratchpad Memory Consumption inMulti-Task Environments.- Feedback-Based Admission Control for Hard Real-TimeTask Allocation under Dynamic Workload on Many-core Systems.- All About Time:Timing, Tracing, and Performance Modeling Data Age Diminution in the LogicalExecution Time Model.- Accurate Sample Time Reconstruction for Sensor DataSynchronization.- DiaSys: On-Chip Trace Analysis for Multi-ProcessorSystem-on-Chip.- Analysis of Intel's Haswell Microarchitecture Using The ECMModel and Microbenchmarks.- Measurement-Based Probabilistic Timing Analysis forGraphics Processor Units.- Approximate and Energy-Efficient Computing.- ReducingEnergy Consumption of Data Transfers using Runtime Data Type Conversion.-Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector.-Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode DecisionProcess Using Actor-based Modeling.- Low-Cost Hardware Infrastructure forRuntime Thread Level Energy Accounting.- Allocation: From