Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
(Sprache: Englisch)
The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter...
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The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.
Inhaltsverzeichnis zu „Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits “
- Dedication- Preface
- Foreword
- Acknowledgments
1. Introduction
2. Functional and Parametric Defect Models
3. Digital CMOS Fault Modeling
4. Defects in Logic Circuits and their Test Implications
5. Testing Defects and Parametric Variations in RAMs
6. Defect Oriented Analog Testing
7. Yield Engineering
8. Conclusions
- Index
Bibliographische Angaben
- Autoren: José Pineda de Gyvez , Manoj Sachdev
- 2nd ed. 2007, 352 Seiten, Maße: 16 x 24,1 cm, Gebunden, Englisch
- Verlag: Springer US
- ISBN-10: 0387465464
- ISBN-13: 9780387465463
- Erscheinungsdatum: 21.06.2007
Sprache:
Englisch
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