Error Correction Codes for Non-Volatile Memories

Preface. Acknowledgements. 1. Basic coding theory. 1.1 Introduction. 1.2 Error detection and correction codes. 1.3 Probability of errors in a transmission channel. 1.4 ECC effect on error probability. 1.5 Basic definitions. Bibliography. 2 Error Correction Codes. 2.1 Hamming codes. 2.2 Reed-Muller codes. 2.3 Cyclic codes. Bibliography. 3 NOR Flash memories. 3.1 Introduction. 3.2 Read. 3.3 Program. 3.4 Erase. Bibliography. 4 NAND Flash memories. 4.1 Introduction. 4.2 Read. 4.3 Program. 4.4 Erase. Bibliography. 5 Reliability of Floating Gate Memories; A.Chimenton, M.Atti, P.Olivo. 5.1 Introduction. 5.2 Reliability issues in floating gate memories. 5.3 Conclusions. Bibliography. 6 Hardware implementation of Galois field operators. 6.1 Gray map. 6.2 Adders. 6.3 Constant multipliers. 6.4 Full multipliers. 6.5 Divider. 6.6 Linear Shift Register. Bibliography. 7 Hamming code for Flash memories. 7.1 Introduction. 7.2 NOR Single Bit. 7.3 NOR Flash multilevel memory. 7.4 Algorithmic Hamming code for big size blocks. Bibliography. 8 Cyclic codes for non volatile storage. 8.1 General structure. 8.2 Encoding. 8.3 Syndromes calculation. 8.4 Finding error locator polynomial. 8.5 Searching polynomial roots. 8.6 Computing error magnitude. 8.7 Decoding failures. 8.8 BCH vs Reed-Solomon. Bibliography. 9 BCH hardware implementation in NAND Flash memories. 9.1 Introduction. 9.2 Scaling of a ECC for MLC memories. 9.3 The system. 9.4 Parity computation. 9.5 Syndrome computation. 9.6 Berlekamp machine. 9.7 The Chien Machine. 9.8 Double Chien machine. 9.9 BCH embedded into the NAND memory. Bibliography. 10 Erasure technique. 10.1 Error disclosing capability for binary BCH codes. 10.2 Erasure concept in memories. 10.3 Binary erasure decoding. 10.4 Erasure and majority decoding. 10.5 Erasure decoding performances. Bibliography. Appendix A: Hamming code. A.1 Routine to find a parity matrix for a single bit or a single cell correction. A.2 Routine to find a parity matrix for a two errors

Rino Micheloni received the Laurea degree (cum laude) in nuclear engineering from the Politecnico of Milan in 1994. From 1995 to 2006 he was with STMicroelectronics where he led the design activities on NOR and NAND Multilevel Flash memories. Currently, he is Senior Principal Engineer for Flash Design at Qimonda. In 2003 he was Co-Guest Editor for the Special Issue of the Proceedings of the IEEE on Flash Memories . Mr. Micheloni has been involved with the following book projects: "VLSI-Design of Non-Volatile Memories, Springer-Verlag, 2005; Chapter 6 in "Floating Gate Devices: Operation and Compact Modeling, Kluwer Academic Publishers, 2004; Chapter 5 in "Flash Memories, Kluwer Academic Publishers, 1999. Mr. Micheloni is a Senior IEEE member and has authored more than 100 patents issued in Europe, Japan and USA. Ravasio Roberto was born in Carvico (BG) in 1966. He graduated at the Politecnico of Milan in 1996. From 1996 to 2000 he worked for Italtel-Siemens as a designer of radiomobile systems. From 2000 to 2006 he was at STMicroelectronics and since 2007 he is working for Qimonda. He has developed NOR and NAND multilevel Flash memories with embedded Hamming and BCH ECC. He is author of several patents and papers.Marelli Alessia was born in Bergamo in 1980. She took her degree in Mathematic Science at Universita
EUR(TM) degli Studi di Milano
EUR" Bicocca with a thesis concerning error correction codes applied to Flash Memories. The thesis work was accompanied with a stage at STMicroelectronics in Agrate Brianza. From 2003 to 2007 she worked at STMicroelectronics taking care of ECC applied to memories and of digital design of Multilevel NAND. From 2007 she works at Qimonda as a digital designer. She is co-author of some patents regarding error correction codes.