Full-Chip Nanometer Routing Techniques

List of Figures. List of Tables. Preface. Acknowledgments. 1. INTRODUCTION. 1 Down to the Wire. 2 Routing Problems. 2.1 Flat Routing Framework. 2.2 Hierarchical Routing Framework. 2.3 Multilevel Routing Framework. 3 Organization of the Book. 3.1 Multilevel Routing Framework. 3.2 Multilevel Full-Chip Routing Considering Crosstalk and Performance. 3.3 Multilevel Full-Chip Routing Considering Antenna Effect Avoidance. 3.4 Multilevel Full-Chip Routing for the X-Based Architecture. 2. ROUTING CHALLENGES FOR NANOMETER TECHNOLOGY. 1 Routing Requirement for the Nanometer Era. 1.1 Signal-Integrity Problems. 1.2 Manufacturability Problems. 3. MULTILEVEL FULL-CHIP ROUTING. 1 Introduction. 2 Elmore Delay Model. 3 Multilevel Routing Framework. 3.1 Performance-Driven Routing Tree Construction. 3.2 Crosstalk-Driven Layer/Track Assignment. 4 Experimental Results. 5 Summary. 4. MULTILEVEL FULL-CHIP ROUTING CONSIDERING ANTENNA EFFECT AVOIDANCE. 1 Introduction. 2 Antenna Effect Damage. 3 Multilevel Routing Framework. 3.1 Bottom-Up Optimal Jumper Prediction. 3.2 Multilevel Routing with Antenna Avoidance. 4 Experimental Results. 5 Summary. 5. MULTILEVEL FULL-CHIP ROUTING FOR THE X-BASED ARCHITECTURE. 1 Introduction. 2 Multilevel X-Routing Framework. 3 X-Architecture Steiner Tree Construction. 3.1 Three-Terminal Net Routing Based on X-Architecture. 3.2 X-Steiner Tree Algorithm by Delaunay Triangulation. 4 Routability-Driven Pattern Routing. 5 Trapezoid-Shaped Track Assignment. 6 Experimental Results. 7 Summary 6. CONCLUDING REMARKS AND FUTURE WORK. 1 Multilevel Routing Framework. 2 Routing Challenges for Nanometer Technology. 3 Multilevel Full-Chip Routing Considering Crosstalk and Performance. 4 Multilevel Full-Chip Routing Considering Antenna Effect Avoidance. 5 Multilevel Full-Chip Routing for the X-Based Architecture. 6 Future Research Directions. References.