Low Power Digital CMOS Design
(Sprache: Englisch)
Power consumption has become a major design consideration for battery-operated, portable systems as well as high-performance, desktop systems. Strict limitations on power dissipation must be met by the designer while still meeting ever higher computational...
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Power consumption has become a major design consideration for battery-operated, portable systems as well as high-performance, desktop systems. Strict limitations on power dissipation must be met by the designer while still meeting ever higher computational requirements. A comprehensive approach is thus required at all levels of system design, ranging from algorithms and architectures to the logic styles and the underlying technology.
Potentially one of the most important techniques involves combining architecture optimization with voltage scaling, allowing a trade-off between silicon area and low-power operation. Architectural optimization enables supply voltages of the order of 1 V using standard CMOS technology. Several techniques can also be used to minimize the switched capacitance, including representation, optimizing signal correlations, minimizing spurious transitions, optimizing sequencing of operations, activity-driven power down, etc. The high- efficiency of DC-DC converter circuitry required for efficient, low-voltage and low-current level operation is described by Stratakos, Sullivan and Sanders. The application of various low-power techniques to a chip set for multimedia applications shows that orders-of-magnitude reduction in power consumption is possible.
The book also features an analysis by Professor Meindl of the fundamental limits of power consumption achievable at all levels of the design hierarchy. Svensson, of ISI, describes emerging adiabatic switching techniques that can break the CV2f barrier and reduce the energy per computation at a fixed voltage. Srivastava, of AT&T, presents the application of aggressive shut-down techniques to microprocessor applications.
Potentially one of the most important techniques involves combining architecture optimization with voltage scaling, allowing a trade-off between silicon area and low-power operation. Architectural optimization enables supply voltages of the order of 1 V using standard CMOS technology. Several techniques can also be used to minimize the switched capacitance, including representation, optimizing signal correlations, minimizing spurious transitions, optimizing sequencing of operations, activity-driven power down, etc. The high- efficiency of DC-DC converter circuitry required for efficient, low-voltage and low-current level operation is described by Stratakos, Sullivan and Sanders. The application of various low-power techniques to a chip set for multimedia applications shows that orders-of-magnitude reduction in power consumption is possible.
The book also features an analysis by Professor Meindl of the fundamental limits of power consumption achievable at all levels of the design hierarchy. Svensson, of ISI, describes emerging adiabatic switching techniques that can break the CV2f barrier and reduce the energy per computation at a fixed voltage. Srivastava, of AT&T, presents the application of aggressive shut-down techniques to microprocessor applications.
Klappentext zu „Low Power Digital CMOS Design “
Power consumption has become a major design consideration for battery-operated, portable systems as well as high-performance, desktop systems. Strict limitations on power dissipation must be met by the designer while still meeting ever higher computational requirements. A comprehensive approach is thus required at all levels of system design, ranging from algorithms and architectures to the logic styles and the underlying technology. Potentially one of the most important techniques involves combining architecture optimization with voltage scaling, allowing a trade-off between silicon area and low-power operation. Architectural optimization enables supply voltages of the order of 1 V using standard CMOS technology. Several techniques can also be used to minimize the switched capacitance, including representation, optimizing signal correlations, minimizing spurious transitions, optimizing sequencing of operations, activity-driven power down, etc. The high- efficiency of DC-DC converter circuitry required for efficient, low-voltage and low-current level operation is described by Stratakos, Sullivan and Sanders. The application of various low-power techniques to a chip set for multimedia applications shows that orders-of-magnitude reduction in power consumption is possible.
The book also features an analysis by Professor Meindl of the fundamental limits of power consumption achievable at all levels of the design hierarchy. Svensson, of ISI, describes emerging adiabatic switching techniques that can break the CV2f barrier and reduce the energy per computation at a fixed voltage. Srivastava, of AT&T, presents the application of aggressive shut-down techniques to microprocessor applications.
Inhaltsverzeichnis zu „Low Power Digital CMOS Design “
1 Introduction.- 1.1 Overview of Book.- 2 Hierarchy of Limits of Power.- 2.1 Introduction.- 2.2 Background.- 2.3 Theoretical Limits.- 2.4 Quasi-Adiabatic Microelectronics.- 2.5 Practical Limits.- 2.6 Conclusion.- 3 Sources of Power Consumption.- 3.1 Switching Component of Power.- 3.2 Short-circuit Component of Power.- 3.3 Leakage Component of Power.- 3.4 Static Power.- 3.5 Summary.- 4 Voltage Scaling Approaches.- 4.1 Reliability-Driven Voltage Scaling.- 4.2 Technology-Driven Voltage Scaling.- 4.3 Energy x Delay Minimum Based Voltage Scaling.- 4.4 Voltage Scaling Through Optimal Transistor Sizing.- 4.5 Voltage Scaling Using Threshold Reduction.- 4.6 Architecture-Driven Voltage Scaling.- 4.7 Summary.- 5 DC Power Supply Design in Portable Systems.- 5.1 Voltage Regulation Enhances System Run-time.- 5.2 DC-DC Converter Topology Selection.- 5.3 Converter Miniaturization.- 5.4 Circuit Optimizations for High Efficiency.- 6 Adiabatic Switching.- 6.1 Adiabatic Charging.- 6.2 Adiabatic Amplification.- 6.3 Adiabatic Logic Gates.- 6.4 Stepwise Charging.- 6.5 Pulsed-Power Supplies.- 6.6 Summary.- 6.7 Acknowledgments.- 7 Minimizing Switched Capacitance.- 7.1 Algorithmic Optimization.- 7.2 Architecture Optimization.- 7.3 Logic Optimization.- 7.4 Circuit Optimization.- 7.5 Physical Design.- 7.6 Summary.- 8 Computer Aided Design Tools.- 8.1 Previous Work.- 8.2 Application of Transformations to Minimize Power.- 8.3 Cost Function.- 8.4 Optimization Algorithm.- 8.5 Examples and Results.- 8.6 Summary.- 9 A Portable Multimedia Terminal.- 9.1 Technology Trends for Low Power Portable Systems.- 9.2 System Partitioning for Low-power.- 9.3 Architecture of the Portable Multimedia Terminal.- 9.4 Low Power Implementation of the I/O Processing Modules.- 9.5 System Implementation.- 9.6 Summary.- 10 LowPower Programmable Computation.- 10.1 Architectural Approaches to Low-power.- 10.2 Shutdown Techniques.- 10.3 Architecture-Driven Voltage Reduction.- 10.4 Summary.- 11 Conclusions.
Bibliographische Angaben
- Autoren: Anantha P. Chandrakasan , Robert W. Brodersen
- 2012, Softcover reprint of the original 1st ed. 1995, XI, 409 Seiten, Maße: 15,7 x 23,4 cm, Kartoniert (TB), Englisch
- Verlag: Springer, Berlin
- ISBN-10: 1461359848
- ISBN-13: 9781461359845
Sprache:
Englisch
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