Low Power Interconnect Design
(Sprache: Englisch)
As well as offering practical solutions for delay and power reduction for on-chip interconnects and buses, this book provides in-depth descriptions of the problem of signal delay and extra power consumption and possible solutions for delays and glitches.
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As well as offering practical solutions for delay and power reduction for on-chip interconnects and buses, this book provides in-depth descriptions of the problem of signal delay and extra power consumption and possible solutions for delays and glitches.
Klappentext zu „Low Power Interconnect Design “
This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system. Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses.
Inhaltsverzeichnis zu „Low Power Interconnect Design “
Part I Basics of Interconnect Design.- Introduction to Interconnects.- CMOS Buffer.- Part II Buffer and Schmidt trigger Insertion Techniques for Low Power Interconnect Design.- Buffer Insertion as a Solution to Interconnect Issues.- Schmidt Trigger Approach.- Part III Bus Coding Techniques for Low Power Interconnect Design.- Bus Coding Techniques.
Bibliographische Angaben
- Autor: Sandeep Saini
- 2015, 2015, XVII, 152 Seiten, 12 farbige Abbildungen, Maße: 16 x 24,1 cm, Gebunden, Englisch
- Verlag: Springer, Berlin
- ISBN-10: 1461413222
- ISBN-13: 9781461413226
Sprache:
Englisch
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