Planar Double-Gate Transistor

Introduction. 1 Multiple Gate Technologies; Thierry Poiroux, Maud Vinet and Simon Deleonibus. 1.1 Introduction. 1.2. Advantages of multiple gate technologies. 1.3. Planar double gate technologies. 1.4. Non planar multiple gate technologies. 1.5. Conclusions and perspectives. References. 2 Compact Modeling of Independent Double-Gate Mosfet: a Physical Approach; Daniela Munteanu and Jean-Luc Autran. 2.1. Introduction. 2.2. Drift-diffusion Drain current modeling. 2.3. Ballistic current in the subthreshold regime. 2.4. Conclusion. References. 3 Compact Modeling of Double Gate MOSFET for IC Design; Marina Reyboz, Olivier Rozeau and Thierry Poiroux. 3.1. Introduction. 3.2. Modeling of Independent Gate MOSFET With Independent Driven Gates. 3.3. Long channel IDG MOSFET Threshold voltage based model. 3.4. Short channel effects. 3.5. Conclusion. References. 4 Low Frequency Noise in Double-Gate SOI CMOS Devices; Jalal Jomaah and Gérard Ghibaudo. 4.1. Introduction. 4.2. Low Frequency Noise Analysis. 4.3. Results and Discussions. 4.4. Conclusion. References. 5 Analog Circuit Design; Philippe Freitas, David Navarro, Ian O'Connor, Gérard Billiot, Hervé Lapuyade and Jean-Baptiste Begueret. 5.1. Double Gate MOSFET In Analog Design. 5.2. Current Mirrors. 5.3. Differential Pairs. 5.4. Low Voltage OTAS. 5.5. High Speed Comparators. 5.6. Conclusion. References. 6 Logic Circuit Design With DGMOS Devices; Ian O'Connor, Ilham Hassoune, Xi Yang and David Navarro. 6.1. DGMOS characteristics and impact on digital design. 6.2. Standard cells using DGMOS. 6.3. Ultra Low Power full-adder using Double gate SOI devices. 6.4. DGMOS DEVICE based reconfigurable cells. References. 7 SRAM CircuitDesign; Bastien Giraud, Olivier Thomas, Amara Amara, Andrei Vladimirescu and Marc Belleville. 7.1. Introduction. 7.2. SRAM memories. 7.3. Double gate 6T SRAM memories. 7.4. Double gate 4T & 5T SRAM memories. References. Conclusion. Appendix. Index.

Prof. Amara AMARA obtained his HDR (Confirmation of Leading Research Capabilities) from Evry University, a Ph.D. in computer science in 1989 and a DEA (MSc) in 1985 in microelectronics and computer science both from Paris VI University.In 1988 he joined IBM research and development laboratory at Corbeil-Essonnes where he was involved in SRAM memory design with advanced CMOS technologies. From 1989 to 1992, he was assistant professor developing microelectronics academic programs for CEMIP (Microelectronic Center of Paris Iles-de-France) and took part actively to the European Research Project ESPRIT. In 1992, he joined ISEP (Paris Institute for Electronics) in charge of the microelectronics laboratory where he headed a team involved in High Speed GaAs VLSI circuit design. Currently, his research interests are mainly focusing on Low Power circuit design techniques and on Ultra Low Voltage SOI circuits design. In 1999, he did a sabbatical at Stanford University where he joined Professor De Micheli's group. Prof. Amara is in charge of the Electronics and Telecommunications Departments at ISEP and since Marsh 2004 Director of Research. He is member of the Board of Directors of "ISEP-Enterprises" Association, member of the LETI/CEA and ICP (Catholic Institute of Paris) Scientific Committees and member of the CEMIP Executive Committee. He initiated and is General Chair of FTFC, a Low Voltage and Low Power Workshop held every two years in Paris. He is member of many Technical Program Committees, he was member of DATE'04 (Design Automation and Test in Europe) Executive Committee, Guest editor of "Annales des Télécommunications" special edition dedicated to SoC for telecommunication and member of the Microelectronics Journal Editorial Board. He will be the General Chair of ICICDT 2008 in Grenoble and ISCAS 2010 in Paris.Prof. Amara published many papers and gave many invited talks and tutorials all around the world. He is currently President-Elect of the IEEE French section,