Substrate Noise Coupling in Mixed-Signal ASICs
(Sprache: Englisch)
The purpose of Substrate Noise Coupling in Mixed-Signal ASICs is to provide an overview of very recent research results in the field of substrate noise analysis and reduction techniques. Much of the reported work has been established as...
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The purpose of Substrate Noise Coupling in Mixed-Signal ASICs is to provide an overview of very recent research results in the field of substrate noise analysis and reduction techniques. Much of the reported work has been established as part of the Mixed-Signal Initiative of the European Union. It is a representative sampling of the current state of the art in this area. All the different aspects of the substrate noise coupling problem are covered. Some chapters describe techniques to model and reduce the digital switching noise injected in the substrate. Other chapters describe methods to analyse the propagation of the noise from the source (the digital circuitry) to the reception point (the embedded analog circuitry) through the substrate considered as a resistive/capacitive mesh. Finally, the remaining chapters describe techniques to model and especially to reduce the impact of substrate noise on the analog side. This is illustrated with several practical design examples and measurement results.
Klappentext zu „Substrate Noise Coupling in Mixed-Signal ASICs “
This book is the first in a series of three dedicated to advanced topics in Mixed-Signal IC design methodologies. It is one of the results achieved by the Mixed-Signal Design Cluster, an initiative launched in 1998 as part of the TARDIS project, funded by the European Commission within the ESPRIT-IV Framework. This initiative aims to promote the development of new design and test methodologies for Mixed-Signal ICs, and to accelerate their adoption by industrial users. As Microelectronics evolves, Mixed-Signal techniques are gaining a significant importance due to the wide spread of applications where an analog front-end is needed to drive a complex digital-processing subsystem. In this sense, Analog and Mixed-Signal circuits are recognized as a bottleneck for the market acceptance of Systems-On-Chip, because of the inherent difficulties involved in the design and test of these circuits. Specially, problems arising from the use of a common substrate for analog and digital components are a main limiting factor. The Mixed-Signal Cluster has been formed by a group of 11 Research and Development projects, plus a specific action to promote the dissemination of design methodologies, techniques, and supporting tools developed within the Cluster projects. The whole action, ending in July 2002, has been assigned an overall budget of more than 8 million EURO.
Inhaltsverzeichnis zu „Substrate Noise Coupling in Mixed-Signal ASICs “
Contributors. Foreword. Projects in the mixed-signal design cluster. Introduction; G.G.E. Gielen, S. Donnay.1. Context.
2. Book overview.
1: Technology impact on substrate noise; F.J.R. Clément.
1. Introduction.
2. Substrate physics.
3. Parasitic substrate effects.
4. Wafer impact.
5. Fabrication processes.
6. Conclusions.
2: Substrate noise generation in complex digital systems; S. Donnay, M. van Heijningen, M. Badaroglu.
1. Introduction.
2. Sources of substrate noise.
3. Substrate modeling.
4. How to measure substrate noise.
5. First mixed-signal test chip with simple inverter chains.
6. Second test chip: a 86-Kgate digital filter bank.
7. Conclusions.
3: Modeling and analysis of substrate noise coupling in mixed-signal ICs; N. Verghese, Wen Kung Chu, J. McCanny.
1. Introduction.
2. Substrate noise analysis methodology.
3. Modeling parasitics.
4. Substrate parasitics.
5. Analysis of substrate noise.
6. Analysis of impact of substrate noise.
7. Substrate noise analysis data flow.
8. A design example.
9. Summary.
4: SPACE for substrate resistance extraction; N.P. van der Meijs.
1. Introduction.
2. Substrate analysis overview.
3. The Boundary Element Method.
4. Parametric modeling method.
5. Combined BEM/FEM Modeling.
6. The SPACE Layout to Circuit Extractor.
7. Conclusion.
5: Models and parameters for crosstalk simulation; V. Liberali.
1. Introduction.
2. Design methodology.
3. Modeling.
4. Parameters.
5. Simulation.
6. Validation of the proposed approach.
7. Conclusion.
6: High-level simulation of substrate noise generation in complex digital systems; M.Badaroglu, M. van Heijningen, S. Donnay.
1. Introduction.
2. Library characterization.
3. Substrate noise simulation.
4. Experimental results.
5. Conclusions.
7: Modeling the impact of digital substrate noise on analog integrated circuits; Y. Zinzius, G. Gielen, W. Sansen.
1. Introduction.
2. Overview of substrate noise impact in analog circuits.
3.
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Modeling the digital substrate noise impact on analog circuits.
4. Measurements of the impact of digital substrate noise on analog designs.
5. Conclusions.
8: Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver; Min Xu, B.A. Wooley.
1. Introduction.
2. General model of the effect of substrate noise on analog circuits.
3. Substrate noise characterization.
4. Noise coupling into the LNA.
5. A statistical approach to substrate noise characterization for digital circuits.
6. Conclusion.
9: A practical approach to modeling silicon-crosstalk in systems-on-silicon; P.T.M. van Zeijl.
1. Introduction.
2. Problem statement.
3. Limitations in state-of-the-art approaches to silicon-crosstalk.
4. Our strategy.
5. Conclusions.
10: The reduction of switching noise using CMOS current steering logic; M. Kayal, R. Lara Saez, M. Pastre.
1. Introduction.
2. Definitions.
3. CSL inverter.
4. CSL NAND and NOR gates.
5. FSCL inverter.
6. Experimental comparison between static logic and CSL.
7. Comparative evaluation of CSL, FSCL and conventional static logic.
8. CSL design and layout CAD tools.
9. Conclusion. 11 : Low-noise digital design techniques; M. Badaroglu, S. Donnay.
1. Introduction.
2. Reducing substrate noise generation.
3. Clock tree with different latencies.
4. Measurements to evaluate the low-noise design techniques.
5. Conclusions.
12: How to deal with substrate bounce in analog circuits in epi-type CMOS technology; B. Nauta, G. Hoogzaad.
1. Introduction.
2. Substrate noise.
3. Problems in analog.
4. Strategy for analog.
5. Examples.
6. Conclusions.
13: Reducing substrate bounce in CMOS RF-circuitry; D.M.W. Leenaerts.
1. Introduction.
2. Substrate bounce due to a sigma-delta modulator.
3. Guard rings on a low-ohmic substrate.
4. Guard rings on a high-ohmic substrate.
5. Substrate bounce in an RF system.
6. Concluding remarks.
4. Measurements of the impact of digital substrate noise on analog designs.
5. Conclusions.
8: Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver; Min Xu, B.A. Wooley.
1. Introduction.
2. General model of the effect of substrate noise on analog circuits.
3. Substrate noise characterization.
4. Noise coupling into the LNA.
5. A statistical approach to substrate noise characterization for digital circuits.
6. Conclusion.
9: A practical approach to modeling silicon-crosstalk in systems-on-silicon; P.T.M. van Zeijl.
1. Introduction.
2. Problem statement.
3. Limitations in state-of-the-art approaches to silicon-crosstalk.
4. Our strategy.
5. Conclusions.
10: The reduction of switching noise using CMOS current steering logic; M. Kayal, R. Lara Saez, M. Pastre.
1. Introduction.
2. Definitions.
3. CSL inverter.
4. CSL NAND and NOR gates.
5. FSCL inverter.
6. Experimental comparison between static logic and CSL.
7. Comparative evaluation of CSL, FSCL and conventional static logic.
8. CSL design and layout CAD tools.
9. Conclusion. 11 : Low-noise digital design techniques; M. Badaroglu, S. Donnay.
1. Introduction.
2. Reducing substrate noise generation.
3. Clock tree with different latencies.
4. Measurements to evaluate the low-noise design techniques.
5. Conclusions.
12: How to deal with substrate bounce in analog circuits in epi-type CMOS technology; B. Nauta, G. Hoogzaad.
1. Introduction.
2. Substrate noise.
3. Problems in analog.
4. Strategy for analog.
5. Examples.
6. Conclusions.
13: Reducing substrate bounce in CMOS RF-circuitry; D.M.W. Leenaerts.
1. Introduction.
2. Substrate bounce due to a sigma-delta modulator.
3. Guard rings on a low-ohmic substrate.
4. Guard rings on a high-ohmic substrate.
5. Substrate bounce in an RF system.
6. Concluding remarks.
... weniger
Bibliographische Angaben
- 2010, XXXI, 287 Seiten, Maße: 15,2 x 22,9 cm, Kartoniert (TB), Englisch
- Herausgegeben: Stéphane Donnay, Georges G. E. Gielen
- Verlag: Springer, Berlin
- ISBN-10: 1441953418
- ISBN-13: 9781441953414
Sprache:
Englisch
Pressezitat
From the reviews: "This book covers modeling and simulation for the noise from substrate. This book reviews the causes of noise in substrate and possible prevention of the noise. ... As a practicing engineer, I feel that their techniques for noise prevention are legitimate and applicable. This book is worthwhile for IC design engineers. Those engineers that work on integration of analog and digital parts may want to read this book to prevent any malfunctioning ICs." (IEEE Circuits & Devices Magazine, Vol. 20 (5), September/October, 2004)
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