Verification by Error Modeling
Using Testing Techniques in Hardware Verification
(Sprache: Englisch)
This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.
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Klappentext zu „Verification by Error Modeling “
This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.
Inhaltsverzeichnis zu „Verification by Error Modeling “
From the contents:1. Introduction
2. Boolean function representations
3. Don't cares and their calculation
4. Testing
5. Design error models
6. Design verification by AT
7. Identifying redundant gate and wire replacements
- Conclusions and further work
- Appendices
- References
- Index
Bibliographische Angaben
- Autoren: Zeljko Zilic , Katarzyna Radecka
- 2003, 236 Seiten, Maße: 16 x 24,1 cm, Gebunden, Englisch
- Verlag: Springer US
- ISBN-10: 1402076525
- ISBN-13: 9781402076527
- Erscheinungsdatum: 30.11.2003
Sprache:
Englisch
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