Wafer Level 3-D ICs Process Technology
(Sprache: Englisch)
This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D...
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Klappentext zu „Wafer Level 3-D ICs Process Technology “
This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.
Inhaltsverzeichnis zu „Wafer Level 3-D ICs Process Technology “
Overview of Wafer Level 3-D ICs.- Monolithic 3-D Integrated Circuits.- Stacked CMOS Technologies.- Wafer Bonding Technologies and Strategies for 3-D ICs.- Through Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies.- Cu Wafer Bonding for 3-D ICs Applications.- Cu/Sn Solid-Liquid Interdiffusion Bonding.- An SOI-Based 3-D Circuit Integration Technology.- 3-D Fabrication Options for High Performance CMOS Technology.- 3-D Integration Based upon Dielectric Adhesive Bonding.- Direct Hybrid Bonding.- 3-D Memory.- Circuit Architectures for 3-D Integration.- Thermal Challenges of 3-D ICs.- Status and Outlook.
Bibliographische Angaben
- 2008, 2009, 410 Seiten, Maße: 16 x 24,1 cm, Gebunden, Englisch
- Herausgegeben:Tan, Chuan Seng; Gutmann, Ronald J.; Reif, L. Rafael
- Herausgegeben: Chuan Seng Tan, L. Rafael Reif, Ronald J. Gutmann
- Verlag: Springer
- ISBN-10: 0387765328
- ISBN-13: 9780387765327
- Erscheinungsdatum: 19.09.2008
Sprache:
Englisch
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