Low Power Networks-on-Chip (PDF)
(Sprache: Englisch)
Low Power Networks-on-Chip
Edited by:
(editors)
Cristina Silvano
Marcello Lajolo
Gianluca Palermo
In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design...
Edited by:
(editors)
Cristina Silvano
Marcello Lajolo
Gianluca Palermo
In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design...
sofort als Download lieferbar
Printausgabe 149.79 €
eBook (pdf) -36%
96.29 €
48 DeutschlandCard Punkte sammeln
- Lastschrift, Kreditkarte, Paypal, Rechnung
- Kostenloser tolino webreader
Produktdetails
Produktinformationen zu „Low Power Networks-on-Chip (PDF)“
Low Power Networks-on-Chip
Edited by:
(editors)
Cristina Silvano
Marcello Lajolo
Gianluca Palermo
In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issues
still represent one of the limiting factors in integrating multi- and many-cores
on a single chip.
This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.
.Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures;
.Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect;
.Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings.
Edited by:
(editors)
Cristina Silvano
Marcello Lajolo
Gianluca Palermo
In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issues
still represent one of the limiting factors in integrating multi- and many-cores
on a single chip.
This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.
.Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures;
.Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect;
.Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings.
Bibliographische Angaben
- 2010, 2011, 287 Seiten, Englisch
- Herausgegeben: Cristina Silvano, Marcello Lajolo, Gianluca Palermo
- Verlag: Springer-Verlag GmbH
- ISBN-10: 144196911X
- ISBN-13: 9781441969118
- Erscheinungsdatum: 24.09.2010
Abhängig von Bildschirmgröße und eingestellter Schriftgröße kann die Seitenzahl auf Ihrem Lesegerät variieren.
eBook Informationen
- Dateiformat: PDF
- Größe: 15 MB
- Ohne Kopierschutz
- Vorlesefunktion
Sprache:
Englisch
Kommentar zu "Low Power Networks-on-Chip"
0 Gebrauchte Artikel zu „Low Power Networks-on-Chip“
Zustand | Preis | Porto | Zahlung | Verkäufer | Rating |
---|
Schreiben Sie einen Kommentar zu "Low Power Networks-on-Chip".
Kommentar verfassen